参数资料
型号: XRT75L00DIV-F
厂商: Exar Corporation
文件页数: 42/92页
文件大小: 0K
描述: IC LIU E3/DS3/STS-1 SGL 52TQFP
标准包装: 96
类型: 线路接口装置(LIU)
驱动器/接收器数: 1/1
规程: DS3,E3,STS-1,SONET
电源电压: 3.135 V ~ 3.465 V
安装类型: 表面贴装
封装/外壳: 52-LQFP
供应商设备封装: 52-TQFP(10x10)
包装: 托盘
XRT75L00D
REV. 1.0.2
E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER
42
8.0
DIAGNOSTIC FEATURES:
8.1
PRBS Generator and Detector:
The XRT75L00D contains an on-chip Pseudo Random Binary Sequence (PRBS) generator and detector for
diagnostic purpose. This feature is only available in Host mode. With the PRBSEN bit = “1”, the transmitter will
send out PRBS of 223-1 in E3 rate or 215-1 in STS-1/DS3 rate. At the same time, the receiver PRBS detector is
also enabled. When the correct PRBS pattern is detected by the receiver, the RNEG/LCV pin will go “Low” to
indicate PRBS synchronization has been achieved. When the PRBS detector is not in sync the PRBSLS bit will
be set to “1” and RNEG/LCV pin will go “High”.
With the PRBS mode enabled, the user can also insert a single bit error by toggling “INSPRBS” bit. This is
done by writing a “1” to INSPRBS bit. The receiver at RNEG/LCV pin will pulse “High” for half RxClk cycle for
every bit error detected. Any subsequent single bit error insertion must be done by first writing a “0” to
INSPRBS bit and followed by a “1”.
When PRBS mode is enabled, the PRBS counter starts counting each single bit error. The PRBS counter is 16
bits wide. The current value in the counter can be read via two readback operations of the Serial I/O registers.
1) Either the Least Significant Byte (LSB, address 0x30) or the Most Significant Byte (MSB, address 0x31) can
be read first. The value of the un-read register will be copied into the Holding register (address 0x38) and both
the LSB and MSB registers will be reset to zero.
2) Read the Holding register and concatenate the result with the value from the first read operation to get the
full 16 bit counter value.
When the PRBS mode is first enabled, errors will be counted while the receiver logic is synchronizing to the
PRBS pattern. When RNEG/LCV goes “Low” indicating PRBS synchronization, reset the counter by reading
either the LSB or the MSB register.
Figure 25 shows the status of RNEG/LCV pin when the XRT75L00D is configured in PRBS mode.
0x32-
0x37
Reserved
0x38
Read
Only
D[7:0]
PRBShold
PRBS Holding Register
0x39-
0x3D
Reserved
0x3E
Read
Only
D[7:0]
Chip_id
This read only register contains device id.
01010001
0x3F
Read
Only
D[7:0]
Chip_version This read only register contains chip version number
00000001
ADDRESS
(HEX)
TYPE
BIT
LOCATION
SYMBOL
DESCRIPTION
DEFAULT
VALUE(BIN)
相关PDF资料
PDF描述
XRT75L00IV-F IC LIU E3/DS3/STS-1 SGL 52TQFP
XRT75L02DIV-F IC LIU E3/DS3/STS-1 2CH 100TQFP
XRT75L03DIV-F IC LIU E3/DS3/STS-1 3CH 128LQFP
XRT75L03IV-F IC LIU E3/DS3/STS-1 3CH 128LQFP
XRT75L04DIV-F IC LIU E3/DS3/STS-1 4CH 176TQFP
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