参数资料
型号: XRT75L00DIV-F
厂商: Exar Corporation
文件页数: 90/92页
文件大小: 0K
描述: IC LIU E3/DS3/STS-1 SGL 52TQFP
标准包装: 96
类型: 线路接口装置(LIU)
驱动器/接收器数: 1/1
规程: DS3,E3,STS-1,SONET
电源电压: 3.135 V ~ 3.465 V
安装类型: 表面贴装
封装/外壳: 52-LQFP
供应商设备封装: 52-TQFP(10x10)
包装: 托盘
XRT75L00D
E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER
REV. 1.0.2
85
NOTE: The user can only disable the "SONET APS Recovery Time Mode" if the LIU is operating in the Host Mode. If the
user is operating the LIU in the Hardware Mode, then the user will have NO ability to disable the "SONET APS
Recovery Time Mode" feature.
9.8.4
How should one configure the LIU, if one needs to support "Daisy-Chain" Testing at the end
Customer’s site?
Daisy-Chain testing is emerging as a new requirements that many of our customers are imposing on our
SONET Mapper and LIU products. Many System Designer/Manufacturers are finding out that whenever their
end-customers that are evaluating and testing out their systems (in order to determine if they wish to move
forward and start purchasing this equipment in volume) are routinely demanding that they be able to test out
these systems with a single piece of test equipment. This means that the end-customer would like to take a
single piece of DS3 or STS-1 test equipment and (with this test equipment) snake the DS3 or STS-1 traffic
(that this test equipment will generate) through many or (preferably all) channels within the system.
For
example, we have had request from our customers that (on a system that supports OC-192) our silicon be able
to support this DS3 or STS-1 traffic snaking through the 192 DS3 or STS-1 ports within this system.
After extensive testing, we have determined that the best approach to complying with test "Daisy-Chain"
Testing requirements, is to configure the Jitter Attenuator blocks (within each of the Channels within the LIU)
into the "32-Bit" Mode. The user can configure the Jitter Attenuator block (within a given channel of the LIU) to
operate in this mode by settings in the table below.
REFERENCES
1. TEST REPORT - AUTOMATIC PROTECTION SWITCHING (APS) RECOVERY TIME TESTING WITH THE
XRT94L43 DS3/E3/STS-1 TO STS-12 MAPPER IC - Revision C Silicon
JITTER ATTENUATOR CONTROL REGISTER
Channel 0 Address Location = 0x07, Channel 1 Address Location = 0x0F, Channel 2 Address Location = 0x17
BIT 7BIT 6BIT 5BIT 4BIT 3
BIT 2BIT 1
BIT 0
Unused
SONET APS
Recovery
Time Disable
Ch_n
JA RESET
Ch_n
JA1 Ch_n
JA in Tx Path
Ch_n
JA0 Ch_n
R/O
R/W
00
000
11
0
相关PDF资料
PDF描述
XRT75L00IV-F IC LIU E3/DS3/STS-1 SGL 52TQFP
XRT75L02DIV-F IC LIU E3/DS3/STS-1 2CH 100TQFP
XRT75L03DIV-F IC LIU E3/DS3/STS-1 3CH 128LQFP
XRT75L03IV-F IC LIU E3/DS3/STS-1 3CH 128LQFP
XRT75L04DIV-F IC LIU E3/DS3/STS-1 4CH 176TQFP
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