XRT83L30IV-F (Exar) PDF资料下载 Datasheet(38/78 页)

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参数资料

型号：	XRT83L30IV-F
厂商：	Exar Corporation
文件页数：	38/78页
文件大小：	0K
描述：	IC LIU LH/SH T1/E1 SGL 64TQFP
标准包装：	160
类型：	线路接口装置（LIU）
驱动器/接收器数：	1/1
规程：	T1，E1
电源电压：	3.135 V ~ 3.465 V
安装类型：	表面贴装
封装/外壳：	64-LQFP
供应商设备封装：	64-TQFP（10x10）
包装：	托盘
其它名称：	1016-1633 XRT83L30IV-F-ND

XRT83L30

REV. 1.0.1

SINGLE-CHANNEL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR

DIGITAL LOOP-BACK (DLOOP)

Digital Loop-Back or Local Loop-Back allows the transmit clock and data to be looped back to the

corresponding receiver output pins through the encoder/decoder and jitter attenuator. In this mode, receive

data and clock are ignored, but the transmit data will be sent to the line uninterrupted. This loop back feature

allows users to configure the line interface as a pure jitter attenuator. The Digital Loop-Back signal flow is

shown in Figure 23.

DUAL LOOP-BACK

Figure 24 depicts the data flow in dual-loopback. In this mode, selecting the jitter attenuator in the transmit

path will have the same result as placing the jitter attenuator in the receive path. In dual Loop-Back mode the

recovered clock and data from the line are looped back through the transmitter to the TTIP and TRING without

passing through the jitter attenuator. The transmit clock and data are looped back through the jitter attenuator

to the RCLK and RPOS/RDATA and RNEG pins.

FIGURE 23. DIGITAL LOOP-BACK MODE WITH JITTER ATTENUATOR SELECTED IN TRANSMIT PATH

FIGURE 24. SIGNAL FLOW IN DUAL LOOP-BACK MODE

Decoder

Timing

Control

Data &

Clock

Recovery

TPOS

TNEG

TCLK

RCLK

RPOS

RNEG

Encoder

TTIP

TRING

RTIP

RRING