参数资料
型号: XRT83L30IV-F
厂商: Exar Corporation
文件页数: 77/78页
文件大小: 0K
描述: IC LIU LH/SH T1/E1 SGL 64TQFP
标准包装: 160
类型: 线路接口装置(LIU)
驱动器/接收器数: 1/1
规程: T1,E1
电源电压: 3.135 V ~ 3.465 V
安装类型: 表面贴装
封装/外壳: 64-LQFP
供应商设备封装: 64-TQFP(10x10)
包装: 托盘
其它名称: 1016-1633
XRT83L30IV-F-ND
XRT83L30
5
SINGLE-CHANNEL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
REV. 1.0.1
PIN DESCRIPTIONS BY FUNCTION
SERIAL INTERFACE
SIGNAL NAME
PIN #
TYPE
DESCRIPTION
HW/HOST
20
I
Mode Control Input
This pin is used for selecting Hardware or Host mode to control the device.
Leave this pin unconnected or tie “High” to select Hardware mode. For Host
mode, this pin must be tied “Low”.
NOTE: Internally pulled “High” with a 50k
resistor.
SDI
EQC4
21
I
Serial Data Input
In Host mode, this pin is the data input for the Serial Interface.
Equalizer Control Input 4
SDO
EQC3
22
O
I
Serial Data Output
In Host mode, this pin is the output “Read” data for the serial interface.
Equalizer Control Input 3
SCLK
EQC2
23
I
Serial Interface Clock Input
In Host mode, this clock signal is used to control data “Read” or “Write” oper-
ation for the Serial Interface. Maximum clock frequency is 20MHz.
Equalizer Control Input 2
CS
EQC1
24
I
Chip Select Input
In Host mode, tie this pin “Low” to enable communication with the device via
the Serial Interface.
Equalizer Control Input 1
INT
EQC0
25
O
I
Interrupt Output (active "Low")
In Host mode, this pin goes “Low” to indicate an alarm condition has
occurred within the device. Interrupt generation can be globally disabled by
setting the GIE bit to “0” in the command control register.
Equalizer Control Input 0
NOTE: This pin is an open drain output and requires an external 10k
pull-
up resistor.
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