参数资料
型号: XRT83VSH28IB
厂商: Exar Corporation
文件页数: 50/75页
文件大小: 0K
描述: IC LIU SH E1 OCTAL 225BGA
标准包装: 84
类型: 线路接口装置(LIU)
驱动器/接收器数: 8/8
规程: T1,E1,J1
电源电压: 3.14 V ~ 3.47 V
安装类型: 表面贴装
封装/外壳: 225-BGA
供应商设备封装: 225-BGA(19x19)
包装: 托盘
XRT83VSH28
51
8-CHANNEL E1 SHORT-HAUL LINE INTERFACE UNIT
REV. 2.0.0
5.7
MICROPROCESSOR INTERFACE TIMING - MCP860 SYNCHRONOUS MODE
In MPC86x mode the active signals are ADDR[17:0], DATA[7:0], CS, RW, WE, DBEN, TA and PCLK. In this
mode all input signals are sampled by the PCLK. For all inputs minimum setup time is 4ns and minimum hold
time is 3ns. Maximum PCLK frequency is 70 MHz.
A READ cycle starts with RW being 'HIGH' and assertion of CS, address is assumed to be stable at this time
since CS is usually derived from the decoding the address bus.
Following falling edge of CS, DBEN is asserted for the READ operation. DBEN must remain asserted until TA
is asserted by the XRT86SH221 device, which indicates DATA from the addressed location is available on the
data bus. DBEN and CS can be de-asserted when the data has been read by the processor. WE should be high
during the entire read cycle.
Operation with wait-states is also possible, provided the wait is longer than the minimum cycle time. Use of TA
is recommended for timing efficiency since the read cycle time can vary depending on the internal address
location being accessed.
WRITE operation is identical to read operation except that the cycle starts with RW being 'LOW', followed by
CS assertion further followed by assertion of WE. Data to be written at the addressed location should be valid
on the data bus at the time WE is asserted. WE should remain asserted until TA is asserted by the
XRT86SH221 device. Following assertion of TA WE and CS may be de-asserted. DBEN should be high during
the entire write cycle.
FIGURE 36. MPC86X MODE TIMING - WRITE OPERATION
Table 18
MPC86X Mode Timing - Write Operation
Test Conditions: TA = 25°C, VCC = 3.3V±5% and 1.8V±5%, unless otherwise specified
Timing
Description
Min.
Typ.
Max.
Units
t23
R/W "Low" to rising edge of PCLK set-up time (Write
Operation)
5-
-
ns
t24
CS "Low" to rising edge of PCLK set-up time
4-
-
ns
t25
Rising edge of PCLK to RDY “High”delay
4-
-
ns
1
10
9
8
7
6
5
4
3
2
PClk
R/W
WE
D[7:0]
OE
RDY
8 PClk Cycles
NOTE: PClk = 33Mhz
A[17:0]
CS
After 1 PClk Cycle
t23
t24
t25
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