参数资料
型号: XRT91L31IQ-F
厂商: Exar Corporation
文件页数: 11/41页
文件大小: 0K
描述: IC TXRX SONET/SDH 8BIT 64QFP
标准包装: 1
类型: 收发器,多路复用器
PLL:
主要目的: 以太网,SONET/SDH
输入: LVCMOS,LVPECL,LVTTL
输出: LVCMOS,LVPECL,LVTTL
电路数: 1
差分 - 输入:输出: 是/是
频率 - 最大: 622.08MHz
电源电压: 3.135 V ~ 3.465 V
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 64-FQFP
供应商设备封装: 64-PQFP(10x10)
包装: 托盘
其它名称: 1016-1361
XRT91L31
19
REV. 1.0.2
STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIVER
2.4
External Receive Loop Filter Capacitors
These external loop filter 0.47
μF non-polarized capacitors provide the necessary components to achieve the
required receiver jitter performance. They must be well isolated to prohibit noise entering the CDR block and
should be placed as close to the pins as much as possible. Figure 6 shows the pin connections and external
loop filter components. These two non-polarized capacitors should be of +/- 10% tolerance.
2.5
Loss Of Signal
XRT91L31 supports internal Loss of Signal detection (LOS) and external LOS detection. The internal Loss of
Signal Detector monitors the incoming data stream and if the incoming data stream has no transition
continuously for more than 128 bit periods, Loss of Signal is declared. This LOS detection will be removed
when the circuit detects 16 transitions in a 128 bit period sliding window. Pulling the corresponding DLOSDIS
signal to a high level will disable the internal LOS detection circuit. The external LOS function is supported by
the LOSEXT input. The Single-Ended LVPECL input usually comes from the optical module through an output
usually called “SD” or “FLAG” which indicates the lack or presence of optical power. Depending on the
manufacturer of these devices, the polarity of this signal can be either active "Low" or active "High". LOSEXT is
an active "Low" signal requiring a low level to assert or invoke a forced LOS. The external LOSEXT input pin
and internal LOS detector are gated to control detection and declaration of Loss of Signal (see Figure 7.)
Whenever LOS is internally detected or an external LOS is asserted thru the LOSEXT pin, and none of the
local loopback loops is enabled, the XRT91L31 will automatically force the receive parallel data output to a
logic state "0" for the entire duration that a LOS condition is declared. This acts as a receive data mute upon
LOS function to prevent random noise from being misinterpreted as valid incoming data.
When the local
loopbacks DLOOP or ALOOP is enabled, then LOS conditions will not mute the RX parallel output.
FIGURE 7. LOS DECLARATION CIRCUIT
During RLOOPS operation, the 91L31 mutes the RLOOPS data going to Tx output upon detection of DLOS
while DLOSDIS is not enabled. During RLOOPS operation, the 91L31 also mutes the RLOOPS data going to
FIGURE 6. EXTERNAL LOOP FILTERS
CAP2N
CAP1N
0.47uF
non-polarized
CAP2P
CAP1P
0.47uF
non-polarized
pin 42
pin 39
pin 40
pin 41
DLOS (internal signal)
DLOSDIS
LOSEXT
ALOOP
‘0’ = No LOS detection: Do not
mute receive parallel data bus
‘1’ = LOS_detection: Mute
receive parallel data bus
RLOOPS
RLPS_D_MUTE
(Internal Signal)
DLOOP
‘0’ = No LOS detection:
Do not mute Tx serial data output
‘1’ = LOS_detection: Mute Tx
serial data output
(Internal Signal)
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XRT91L31IQ-F 制造商:Exar Corporation 功能描述:SONET Transceiver IC
XRT91L31IQTR 功能描述:总线收发器 SONET/SDH, FULL DPLX 3.3V I/O, LOS, CMU RoHS:否 制造商:Fairchild Semiconductor 逻辑类型:CMOS 逻辑系列:74VCX 每芯片的通道数量:16 输入电平:CMOS 输出电平:CMOS 输出类型:3-State 高电平输出电流:- 24 mA 低电平输出电流:24 mA 传播延迟时间:6.2 ns 电源电压-最大:2.7 V, 3.6 V 电源电压-最小:1.65 V, 2.3 V 最大工作温度:+ 85 C 封装 / 箱体:TSSOP-48 封装:Reel
XRT91L31IQTR-F 功能描述:总线收发器 SONET/SDH, FULL DPLX 3.3V I/O, LOS, CMU RoHS:否 制造商:Fairchild Semiconductor 逻辑类型:CMOS 逻辑系列:74VCX 每芯片的通道数量:16 输入电平:CMOS 输出电平:CMOS 输出类型:3-State 高电平输出电流:- 24 mA 低电平输出电流:24 mA 传播延迟时间:6.2 ns 电源电压-最大:2.7 V, 3.6 V 电源电压-最小:1.65 V, 2.3 V 最大工作温度:+ 85 C 封装 / 箱体:TSSOP-48 封装:Reel
XRT91L32 制造商:EXAR 制造商全称:EXAR 功能描述:STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIVER
XRT91L32ES 功能描述:LIN 收发器 SONET SDH 8 bit TRANCEIVER RoHS:否 制造商:NXP Semiconductors 工作电源电压: 电源电流: 最大工作温度: 封装 / 箱体:SO-8