参数资料
型号: XRT91L31IQ-F
厂商: Exar Corporation
文件页数: 13/41页
文件大小: 0K
描述: IC TXRX SONET/SDH 8BIT 64QFP
标准包装: 1
类型: 收发器,多路复用器
PLL:
主要目的: 以太网,SONET/SDH
输入: LVCMOS,LVPECL,LVTTL
输出: LVCMOS,LVPECL,LVTTL
电路数: 1
差分 - 输入:输出: 是/是
频率 - 最大: 622.08MHz
电源电压: 3.135 V ~ 3.465 V
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 64-FQFP
供应商设备封装: 64-PQFP(10x10)
包装: 托盘
其它名称: 1016-1361
XRT91L31
20
STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIVER
REV. 1.0.2
Tx output while the LOSEXT input is set to a “LOW” state. Note that the DLOSDIS control pin has no impact
on the CDR muting function due to LOSEXT. DLOSDIS only applies to muting as a result of DLOS detection.
Also, note that serial muting function (RLPS_D_MUTE) only impacts RLOOPS data going to Tx output.
2.6
SONET Frame Boundary Detection and Byte Alignment Recovery
A Frame and Byte Boundary Detection circuit searches the incoming data channel for three consecutive A1
(0xF6 Hex) bytes followed by three consecutive A2 (0x28 Hex) bytes. The detector operates under the control
of the OOF (Out of Frame) signals provided from the SONET Framer. Detection is enabled when OOF is held
"High" and remains active until OOF goes "Low." When framing pattern detection is enabled, the framing
pattern is used to locate byte and frame boundaries in the incoming receive data stream. The receive serial-to-
parallel converter block uses the located byte boundary to assemble the incoming data stream into bytes for
output on the parallel data output bus RXDO[7:0]. The frame boundary is reported on the frame pulse
(FRAMEPULSE) output at the onset of detecting the third A2 byte pattern when any serial 48-bit pattern
matching the framing pattern is detected on the incoming data stream. While in the pattern search and
detection state and so long is OOF is active, the frame pulse (FRAMEPULSE) output is activated for one byte
clock cycle (RXPCLKO = 12.86 ns pulse duration for STS-12/STM-4 or 51.44 ns pulse duration for STS-3/
STM-1) anytime a 48-bit pattern matching the framing pattern is detected on the incoming data stream. Once
the SONET Framer Overhead Circuitry has verified that frame and byte synchronization are correct, the OOF
input pin should be de-asserted by the SONET Framer to disable the XRT91L31 frame search process from
trying to synchronize repeatedly and to de-activate FRAMEPULSE. When the XRT91L31’s framing pattern
detection is disabled upon the de-assertion of OOF input pin from the SONET Framer, the byte boundary will
lock to the detected location and will remain locked to that location found when detection was previously
enabled.
2.7
Receive Serial Input to Parallel Output (SIPO)
During STS-12/STM-4 operation, the SIPO is used to convert the 622.08 Mbps serial data input to 77.76 Mbps
parallel data output which can interface to a SONET Framer/ASIC. If the XRT91L31 is operating in STS-3/
STM-1, the SIPO will convert the 155.52 Mbps serial data input to 19.44 Mbps parallel data output. The SIPO
bit de-interleaves the serial data input into an 8-bit parallel output to RXDO[7:0]. A simplified block diagram is
shown in Figure 8. XRT91L31 clocks data out on RXDO[7:0] at the falling edge of RXPCLKO.
FIGURE 8. SIMPLIFIED BLOCK DIAGRAM OF SIPO
b00
b01
b02
b03
bn0
bn1
bn2
bn3
bn+0
bn+1
bn+2
bn+3
b70
b71
b72
b73
8-bit Parallel LVTTL Output Data
RXDO0
RXDO7
RXDOn+
RXDOn
RXIP/N
RXPCLKO
b30b20b10b00
b70b60b50b40
b33b23b13
b43
b53
b63
b73
SIPO
77.76 MHz (STS-12/STM-4) or 19.44 MHz (STS-3/STM-1)
622.08 Mbps STS-12/STM-4 or
155.52 Mbps STS-3/STM-1 serial data rate
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XRT91L31IQ-F 制造商:Exar Corporation 功能描述:SONET Transceiver IC
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XRT91L32ES 功能描述:LIN 收发器 SONET SDH 8 bit TRANCEIVER RoHS:否 制造商:NXP Semiconductors 工作电源电压: 电源电流: 最大工作温度: 封装 / 箱体:SO-8