参数资料
型号: XRT91L31IQ-F
厂商: Exar Corporation
文件页数: 9/41页
文件大小: 0K
描述: IC TXRX SONET/SDH 8BIT 64QFP
标准包装: 1
类型: 收发器,多路复用器
PLL:
主要目的: 以太网,SONET/SDH
输入: LVCMOS,LVPECL,LVTTL
输出: LVCMOS,LVPECL,LVTTL
电路数: 1
差分 - 输入:输出: 是/是
频率 - 最大: 622.08MHz
电源电压: 3.135 V ~ 3.465 V
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 64-FQFP
供应商设备封装: 64-PQFP(10x10)
包装: 托盘
其它名称: 1016-1361
XRT91L31
17
REV. 1.0.2
STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIVER
2.3
Receive Clock and Data Recovery
The clock and data recovery (CDR) unit accepts the high speed NRZ serial data from the Differential LVPECL
receiver and generates a clock that is the same frequency as the incoming data. The clock recovery can either
utilize the transmitter’s CMU reference clock from either REFCLKP/N or TTLREFCLK (+/- 20ppm) or it can use
independent clock source CDRAUXREFCLK (+/- 200ppm) to train and monitor its clock recovery PLL. Initially
upon startup, the PLL locks to the local reference clock. Once this is achieved, the PLL then attempts to lock
onto the incoming receive data stream. Whenever the recovered clock frequency deviates from the local
reference clock frequency by more than approximately ±500 ppm, the clock recovery PLL will switch and lock
back onto the local reference clock. Whenever a Loss of Lock or a Loss of Signal event occurs, the CDR will
continue to supply a receive clock (based on the local reference) to the framer/mapper device. When the
LOSEXT is asserted by the optical module or when LOS is detected, the receive parallel data output will be
forced to a logic zero state for the entire duration that a LOS condition is detected. This acts as a receive data
mute upon LOS function to prevent random noise from being misinterpreted as valid incoming data. When the
LOSEXT becomes inactive and the recovered clock is determined to be within ±500 ppm accuracy with respect
to the local reference source and LOS is no longer declared, the clock recovery PLL will switch and lock back
onto the incoming receive data stream. Table 7 shows Clock and Data Recovery reference clock settings.
Table 8 specifies the Clock and Data Recovery Unit performance characteristics.
TABLE 7: CLOCK DATA RECOVERY UNIT REFERENCE CLOCK SETTINGS
1Requires frequency accuracy better than +/- 20 ppm in order for the transmitted data rate frequency
to have the necessary accuracy required for SONET systems.
2CDRAUXREFCLK requires accuracy of 77.76 MHz +/- 200 ppm.
2.3.1
Internal Clock and Data Recovery Bypass
Optionally, the internal CDR unit can be disabled and bypassed in lieu of an externally recovered clock.
Asserting the CDRDIS "High" disables the internal Clock and Data Recovery unit and the received serial data
bypasses the integrated CDR block. RXINP/N is then sampled on the rising edge of the externally recovered
CMUFREQSEL CDRREFSEL
STS12/
STS3
REFCLKP/N1OR
TTLREFCLK1
FREQUENCY (MHZ)
CDRAUXREFCLK2
FREQUENCY (MHZ)
CDR OUTPUT
FREQUENCY (MHZ)
0
77.76 MHz
not used
155.52
0
1
77.76 MHz
not used
622.08
1
0
19.44 MHz
not used
155.52
1
0
1
19.44 MHz
not used
622.08
X
1
0
not referenced by CDR
77.76 MHz
155.52
X
1
not referenced by CDR
77.76 MHz
622.08
TABLE 8: CDR AUXREFCLK REFERENCE FREQUENCY REQUIREMENT FOR CLOCK AND DATA RECOVERY
NAME
PARAMETER
MIN
TYP
MAX
UNITS
REFDUTY
Reference clock duty cycle
40
60
%
REFTOL
Reference clock frequency tolerance
-200
+200
ppm
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