XRT94L43
14
REV. 1.0.2
SONET/SDH OC-12 TO 12XDS3/E3 MAPPER
L4
RXL_DATA_N
I
LVPECL
Receive STS-12/STM-4 Data - Negative Polarity PECL Input:
This input pin, along with RXL_DATA_P functions as the Recov-
ered Data Input, from a System back-plane or an Optical Trans-
ceiver. The Receive STS-12/STM-4 Interface block will sample the
data applied to these input pins, upon the rising edge of the
RXL_CLKL_P (and the falling edge of the RXL_CLKL_N) signals.
NOTE: For APS (Automatic Protection Switching) purposes, this
input pin, along with RXL_DATA_P functions as the
Primary Receive Data Input Port.
K3
RXL_DATA_R_P
I
LVPECL
Receive STS-12/STM-4 Data - Positive Polarity PECL Input -
Redundant Port:
This input pin, along with RXL_DATA_R_N functions as the Recov-
ered Data Input, from a System back-plane or an Optical Trans-
ceiver. The Receive STS-12/STM-4 Interface block will sample the
data applied to these input pins, upon the rising edge of the
RXL_CLKL_R_P (and the falling edge of the RXL_CLKL_R_N) sig-
nals.
NOTE: For APS (Automatic Protection Switching) purposes, this
input pin, along with RXL_DATA_R_N functions as the
Redundant Receive Data Input Port.
L3
RXL_DATA_R_N
I
LVPECL
Receive STS-12/STM-4 Data - Negative Polarity PECL Input -
Redundant Port:
This input pin, along with RXL_DATA_R_P functions as the Recov-
ered Data Input, from a System back-plane or an Optical Trans-
ceiver. The Receive STS-12/STM-4 Interface block will sample the
data applied to these input pins, upon the rising edge of the
RXL_CLKL_R_P (and the falling edge of the RXL_CLKL_R_N) sig-
nals.
NOTE: For APS (Automatic Protection Switching) purposes, this
input pin, along with RXL_DATA_R_N functions as the
Redundant Receive Data Input Port.
T3
TXL_CLKI_P
I
LVPECL
Transmit Reference Clock - Positive Polarity PECL Input:
This input pin, along with TxL_CLKI_N can be configured to func-
tion as the timing source for the STS-12/STM-4 Transmit Interface
Block.
If these two input pins are configured to function as the timing
source, then a 622.08MHz clock signal must be applied to these
input pins in the form of a PECL signal. These two inputs can be
configured to function as the timing source by writing the appropri-
ate data into the Interface Control Register - Byte 2 (Indirect
Address = 0x00, 0x31), (Direct Address = 0x0131).
SONET/SDH SERIAL LINE INTERFACE PINS
PIN #SIGNAL NAME
I/O
SIGNAL
TYPE
DESCRIPTION