XRT94L43
3
SONET/SDH OC-12 TO 12XDS3/E3 MAPPER
REV. 1.0.2
FIGURE 2. BLOCK DIAGRAM OF THE XRT94L43 WHEN CONFIGURED IN SDH/TUG-3 MODE
FIGURE 3. BLOCK DIAGRAM OF THE XRT94L43 WHEN CONFIGURED IN SDH/AU-3 MODE
DS3/E3
Framer
Block
DS3/E3
Framer
Block
Rx VC-3
Pointer
Justification
Block
RxVC-3
Pointer
Justification
Block
RxSTM-0
VC-3POH
Block
Rx STM-0
VC-3 POH
Block
Tx STM-0
VC-3POH
Block
Tx STM-0
VC-3 POH
Block
Tx VC-3
Pointer
Justification
Block
TxVC-3
Pointer
Justification
Block
TxSTM-0
SOH
Block
TxSTM-0
SOH
Block
RxSTM-0
SOH
Block
Rx STM-0
SOH
Block
DS3/E3
Jitter
Attenuator
Block
DS3/E3
Jitter
Attenuator
Block
DS3/E3
Mapper
Block
DS3/E3
Mapper
Block
Tx AU-3
Mapper/VC-3
POH
Processor
Block
Tx AU-3
Mapper/VC-3
POH
Processor
Block
TxSTM-4
SOHProcessor
Block
Tx STM-4
SOHProcessor
Block
STM-4
TelecomBus
Block
STM-4
TelecomBus
Block
SERDES
Block
(Primary)
SERDES
Block
(Primary)
SERDES
Block
(APS)
SERDES
Block
(APS)
ClockSynthesizer Block
Clock Synthesizer Block
Channel 1
ToChannels 2–12
Microprocessor Interface
JTAGTest Port
Rx AU-3
Mapper/VC-3
POH
Processor
Block
Rx AU-3
Mapper/VC-3
POH
Processor
Block
Rx STM-4SOH
Processor
Block
Rx STM-4 SOH
Processor
Block
FromChannels2 –12
DS3/E3
Framer
Block
DS3/E3
Framer
Block
Rx VC-3
Pointer
Justification
Block
RxVC-3
Pointer
Justification
Block
RxSTM-0
VC-3POH
Block
Rx STM-0
VC-3 POH
Block
Tx STM-0
VC-3POH
Block
Tx STM-0
VC-3 POH
Block
Tx VC-3
Pointer
Justification
Block
TxVC-3
Pointer
Justification
Block
TxSTM-0
SOH
Block
TxSTM-0
SOH
Block
RxSTM-0
SOH
Block
Rx STM-0
SOH
Block
DS3/E3
Jitter
Attenuator
Block
DS3/E3
Jitter
Attenuator
Block
DS3/E3
Mapper
Block
DS3/E3
Mapper
Block
Tx AU-3
Mapper/VC-3
POH
Processor
Block
Tx AU-3
Mapper/VC-3
POH
Processor
Block
TxSTM-4
SOHProcessor
Block
Tx STM-4
SOHProcessor
Block
STM-4
TelecomBus
Block
STM-4
TelecomBus
Block
SERDES
Block
(Primary)
SERDES
Block
(Primary)
SERDES
Block
(APS)
SERDES
Block
(APS)
ClockSynthesizer Block
Clock Synthesizer Block
Channel 1
ToChannels 2–12
Microprocessor Interface
JTAGTest Port
Rx AU-3
Mapper/VC-3
POH
Processor
Block
Rx AU-3
Mapper/VC-3
POH
Processor
Block
Rx STM-4SOH
Processor
Block
Rx STM-4 SOH
Processor
Block
FromChannels2 –12
DS3/E3
Framer
Block
DS3/E3
Framer
Block
RxSTS-1
Pointer
Justification
Block
Rx STS-1
Pointer
Justification
Block
RxSTS-1
POH
Block
RxSTS-1
POH
Block
TxSTS-1
POH
Block
Tx STS-1
POH
Block
Tx STS-1
Pointer
Justification
Block
TxSTS-1
Pointer
Justification
Block
TxSTS-1
TOH
Block
TxSTS-1
TOH
Block
RxSTS-1
TOH
Block
RxSTS-1
TOH
Block
DS3/E3
Jitter
Attenuator
Block
DS3/E3
Jitter
Attenuator
Block
DS3/E3
Mapper
Block
DS3/E3
Mapper
Block
TxSONET
POH
Processor
Block
TxSONET
POH
Processor
Block
TxSTS-12
TOHProcessor
Block
Tx STS-12
TOHProcessor
Block
STS-12
TelecomBus
Block
STS-12
TelecomBus
Block
SERDES
Block
(Primary)
SERDES
Block
(Primary)
SERDES
Block
(APS)
SERDES
Block
(APS)
Clock Synthesizer Block
ClockSynthesizer Block
Channel 1
ToChannels2–12
Microprocessor Interface
JTAGTest Port
RxSONET
POH
Processor
Block
RxSONET
POH
Processor
Block
RxSTS-12TOH
Processor
Block
RxSTS-12TOH
Processor
Block
FromChannels2–12
DS3/E3
Framer
Block
DS3/E3
Framer
Block
RxSTS-1
Pointer
Justification
Block
Rx STS-1
Pointer
Justification
Block
RxSTS-1
POH
Block
RxSTS-1
POH
Block
TxSTS-1
POH
Block
Tx STS-1
POH
Block
Tx STS-1
Pointer
Justification
Block
TxSTS-1
Pointer
Justification
Block
TxSTS-1
TOH
Block
TxSTS-1
TOH
Block
RxSTS-1
TOH
Block
RxSTS-1
TOH
Block
DS3/E3
Jitter
Attenuator
Block
DS3/E3
Jitter
Attenuator
Block
DS3/E3
Mapper
Block
DS3/E3
Mapper
Block
TxSONET
POH
Processor
Block
TxSONET
POH
Processor
Block
TxSTS-12
TOHProcessor
Block
Tx STS-12
TOHProcessor
Block
STS-12
TelecomBus
Block
STS-12
TelecomBus
Block
SERDES
Block
(Primary)
SERDES
Block
(Primary)
SERDES
Block
(APS)
SERDES
Block
(APS)
Clock Synthesizer Block
ClockSynthesizer Block
Channel 1
ToChannels2–12
Microprocessor Interface
JTAGTest Port
RxSONET
POH
Processor
Block
RxSONET
POH
Processor
Block
RxSTS-12TOH
Processor
Block
RxSTS-12TOH
Processor
Block
FromChannels2–12