
XRT94L43
113
SONET/SDH OC-12 TO 12XDS3/E3 MAPPER
REV. 1.0.2
H25
STS3RxD_D_1_7
DS3/E3/
STS1_Clk_OUT_9
RxSBData_7
O
CMOS
Receive STS-3/STM-1 Telecom Bus - Channel 1 - Output Data Bus
Pin Number 7/DS3/E3 Framer or Transmit STS-1 TOH Processor
block line interface clock output Pin - Channel 9: (DS3/E3/
STS1_CLK_OUT_9):
The function of this output pin depends upon whether or not theSTS-3/
STM-1 Telecom Bus Interface, associated with Channel 1 is enabled.
If STS-3/STM-1 Telecom Bus (Channel 1) has been enabled - STS-3/
STM-1 Receive Telecom Bus - Output Data bus Pin Number 7:
STSRxD_D_1_7:
This output pin along with STS3RxD_D_1[6:0] function as the STS-3/
STM-1 Receive (Drop) Telecom Bus - Output Data Bus for Channel 1.
The STS-3/STM-1 Telecom Bus Interface will update the data via this
output upon the rising edge of STS3RxD_CLK_1.
NOTE: This output pin functions as the MSB (Most Significant Bit) for the
STS-3/STM-1 Receive (Drop) Telecom Bus Interface - Output
Data Bus (Channel 1).
If STS-3/STM-1 Telecom Bus (Channel 1) is disabled - DS3/E3/
STS1_CLK_OUT Line Interface Clock output Pin - Channel 9:
This pin outputs a DS3, E3 or STS-1 rate clock signal to a DS3/E3/STS-1
LIU IC. This output pin should be connected to the TxCLK input of the
DS3/E3/STS-1 LIU IC (corresponding to Channel 9).
By default, the data, which is being output via the DS3/E3/
STS1_DATA_OUT_9 output pin will be updated upon the rising edge of
this clock output pin.
For DS3/E3 Applications
The XRT94L43 can be configured to update the DS3/E3/STS1_DATA_9
output signal upon the falling edge of the DS3/E3/STS1_CLK_9 signal by
setting Bit 0 (DS3/E3/STS1_CLK_OUT Invert), within the I/O Control
Register - Channel 9 (Indirect Address = 0xAE, 0x01), (Direct Address =
0xAF01) to a "1".
For STS-1 Applications
The XRT94L43 can not be configured to update the DS3/E3/
STS1_DATA_OUT_9 signal upon the falling edge of DS3/E3/
STS1_CLK_9.
STS-3/STM-1 TELECOM BUS INTERFACE - RECEIVE DIRECTION
PIN #SIGNAL NAME
I/O
SIGNAL
TYPE
DESCRIPTION