XRT94L43
216
REV. 1.0.2
SONET/SDH OC-12 TO 12XDS3/E3 MAPPER
AB16
STS3TxA_D_3_7
DS3/E3/
STS1_Clk_IN_11
TxSBData_7
I
TTL
Transmit STS-3/STM-1 Telecom Bus - Channel 3 - Input Data Bus
Pin Number 7/DS3/E3 Framer or Receive STS-1 TOH Processor
block line interface clock input Pin - Channel 11:
The function of this pin depends upon whether or not theSTS-3/STM-
1 Telecom Bus Interface, associated with Channel 3 is enabled.
If STS-3/STM-1 Telecom Bus (Channel 3) has been enabled -
STS-3/STM-1 Transmit Telecom Bus - Input Data Bus Pin Num-
ber 7: STS3TxA_D_3_7:
This input pin along with STS3TxA_D_3[6:0] function as the STS-3/
STM-1 Transmit (Add) Telecom Bus - Input Data Bus for Channel 3.
The STS-3/STM-1 Telecom Bus interface will sample and latch this
pin upon the falling edge of STS3TxA_CLK_3.
NOTE: This input pin functions as the MSB (Most Significant Bit) of
the Transmit (Add) Telecom Bus, for Channel 3.
If STS-3/STM-1 Telecom Bus (Channel 3) is disabled - DS3/E3/
STS1_CLK_IN - DS3/E3/STS-1 Line Interface Clock Input - Chan-
nel 11:
This input accepts a recovered DS3, E3 or STS-1 clock signal (from
a DS3/E3/STS-1 LIU IC). This input pin should be connected to the
RCLK output of the DS3/E3/STS-1 LIU IC (corresponding to channel
11). The XRT94L43 uses this clock signal to sample and latch the
data that is applied to the DS3/E3/STS1_DATA_IN_11 input pin num-
ber AD16.
By default, the data that is applied to the DS3/E3/STS1_DATA_IN_11
input pin will be latched into the XRT94L43 upon the falling edge of
this clock signal.
For DS3/E3 Applications
The XRT94L43 can be configured to latch the DS3/E3/
STS1_DATA_IN_11 signal upon the rising edge of this clock signal
by setting Bit 1 (DS3/E3/STS1_CLK_IN Invert), within the I/O Control
Register - Channel 11 (Indirect Address = 0xCE, 0x01), (Direct
Address = 0xCF01) to a "1".
For STS-1 Applications
The XRT94L43 can not be configured to sample the DS3/E3/
STS1_DATA_IN_11 signal upon the rising edge of this clock signal.
STS-3/STM-1 TELECOM BUS INTERFACE - TRANSMIT DIRECTION
PIN #SIGNAL NAME
I/O
SIGNAL
TYPE
DESCRIPTION