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参数资料
| 型号： | ZIF600 |
| 厂商： | ZARLINK SEMICONDUCTOR INC |
| 元件分类： | 寻呼电路 |
| 英文描述： | Pager Synthesiser and 4FSK Demodulator |
| 中文描述： | TELECOM, PAGING DECODER, PDSO24 |
| 封装： | QSOP-24 |
| 文件页数： | 2/9页 |
| 文件大小： | 229K |
| 代理商： | ZIF600 |
1
ZIF600
ZIF600
The ZIF600 synthesiser is for channel selection in 4FSK
pagers. A reference frequency is generated by an on-chip
crystal oscillator with an AFC external trimming varacator
controlled by a DAC.
The ZIF600 digital demodulator uses DSP techniques to
optimise the data extraction in the presence of noise and also
generates an AFC output to adjust the crystal frequency.
Separate power controls allow the system current
consumption to be minimised. All functions are controlled by a
serial bus with a simple programming format and with four
control pins which are used to control the power up and power
down functions of the blocks to allow sequenced wake up and
optimised power consumption.
FEATURES
I
Low Voltage Operation, 2.7 to 3.3V
I
On-chip Reference Oscillator
I
Channel Select Synthesiser
I
Direct VCO input at up to 330MHz
I
6400 Baud Digital 4FSK Demodulator
I
Serial Control Bus
I
Very Low Power Consumption
I
Small QSOP24 Package
Fig.1 Pin connections - top view
APPLICATIONS
I
Pagers - including small form factor designs such as
credit card pagers, watch pagers and PCMCIA
applications
I
Low data rate receivers - security/remote control
QP24
ABSOLUTE MAXIMUM RATINGS
To be defined.
Fig.2 ZIF600 block diagram
ZIF600
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
RXQ
RXI
SRF
DATA0
DATA1
VSSD
VDDD
VREF
RBIAS
PDOUT
PLLC
DACOUT
DSC2
DSC1
DATA
LE
CLOCK
VSSA
VCOFIN
VDDA
REFOSCB
TSS
REFOSC
VSSI
RXI
RXQ
PHASE
DETECTOR
CONTROL LOGIC &
POWER MANAGEMENT
DSC2
DATA1
REFOSC
REFOSB
VCOFIN
DATA
CLOCK
VDDA
VDDD
TSS
VSSA
PLLC
SRF
VSSI
BIASES
VREF
RBIAS
DATA
SLICER
AFC
(DAC)
DIGITAL DEMODULATOR
REFERENCE
DIVIDER
M AND A
DIVIDERS
LE
DSC1
DACOUT
PDOUT
DATA0
TWO MODULUS
PRESCALER
VSSD
LIMI
LIMQ
Demod. Clock
Pager Synthesiser and 4FSK Demodulator
DS4771 - 1.2 October 1997
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