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参数资料
| 型号： | ZIF600 |
| 厂商： | ZARLINK SEMICONDUCTOR INC |
| 元件分类： | 寻呼电路 |
| 英文描述： | Pager Synthesiser and 4FSK Demodulator |
| 中文描述： | TELECOM, PAGING DECODER, PDSO24 |
| 封装： | QSOP-24 |
| 文件页数： | 4/9页 |
| 文件大小： | 229K |
| 代理商： | ZIF600 |
3
ZIF600
FUNCTIONAL DESCRIPTION
The ZIF600 synthesiser is used to select the channel in
4FSK paging receivers and uses on-chip constant current
charge pumps to drive an external passive loop filter. Common
low cost reference crystals are used, at frequencies of 12.8 or
14.4MHz, and are divided to give the required 12.5, 20 or
25kHz channel spacings. The reference crystal oscillator uses
external trimming to meet system requirements and is controlled
by a DAC set by the digital demodulator.
The digital demodulator takes the limited I and Q signals
from the radio receiver and converts the 4-level FSK into 2 bit
data output on pins DATA0 and DATA1. An AFC output from
this demodulator is also included.
Functions are controlled by a serial bus with a simple
programming format and with four control pins to allow optimum
power up sequences which help minimise the system current
consumption.
Crystal
Comp.
Total
MHz
freq. kHz division
12.8
25
512
14.4
25
576
12.8
20
640
14.4
20
720
12.8
12.5
1024
14.4
12.5
1152
12.8
10
1280
14.4
10
1440
DESCRIPTION OF FUNCTIONS
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
Pin Name
RXQ
RXI
SRF
DATA0
DATA1
VSSD
VDDD
VREF
RBIAS
PDOUT
PLLC
DACOUT
VSS1
REFOSC
TSS
REFOSCB
VDDA
VCOFIN
VSSA
CLOCK
LE
DATA
DSC1
DSC2
Pin Type
In
In
In
Out
Out
G
P
In
In
Out
In
Out
G
I/O
In
I/O
P
In
G
In
In
In
In
In
Description
Receiver "Quadrature" output
Receiver "In Phase" output
Symbol Rate Filter
Data output to decoder
Data output to decoder
Digital Ground
2.7 to 3.3V Digital Power Supply
1.25 Volt Reference from ZIF100
Bias setting Resistor 120k
to VSSA max. parasitic capacitance = 5pF
Charge pump output from synthesiser
Synthesiser power down
Trim DAC for crystal
Ground (substrate)
Reference Oscillator
Test Scan Select, Normally logic 0
Reference Oscillator. External resistor to VDD1
2.7 to 3.3V Analog Power Supply
VCO frequency input to synthesiser
Analog Ground
Control Bus Clock
Control Bus Latch Enable
Control Bus Data
With DSC2 controls the operating mode of the demodulator
With DSC1 controls the operating mode of the demodulator
Table 1. List of pins
REFERENCE DIVIDERS
The reference frequency generated by the oscillator on
pins REFOSC and REFOSCB is divided to give the comparison
frequency clock. See Fig. 3.
Ratio selection is five control bits RD1 (where LOW gives
÷
8 mode), RD2 (where LOW gives
÷
4 mode) and RD3 (where
LOW gives
÷
2 mode) which can be set to give the 8 options
needed to get 10kHz, 12.5kHz, 20kHz or 25kHz from either a
12.8 or 14.4MHz crystal, as in Table 2. The additional control
bits RD4 and RD5 allow the option of further division to allow
for an off chip frequency multiplier. If both RD4 and RD5 are set
low then this division stage is bypassed. Other settings for RD4
and RD5 offer division by 2, 3 or 4. Table 3 shows the additional
division options available from RD4 and RD5.
Power down options are available for both the synthesiser
and demodulator, however the crystal oscillator and the
reference divider must be kept running to give a timing signal
to the demodulator whilst the demodulator is on.
Table 2 Reference divider ratios
RD1
RD2
RD3
0
1
0
1
0
1
0
1
0
0
1
1
0
0
1
1
0
0
0
0
1
1
1
1
Table 3 Additional divider ratios
Additional division
RD4
RD5
Bypass
2
3
4
0
0
1
1
0
1
0
1
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