参数资料
型号: ZIF600
厂商: ZARLINK SEMICONDUCTOR INC
元件分类: 寻呼电路
英文描述: Pager Synthesiser and 4FSK Demodulator
中文描述: TELECOM, PAGING DECODER, PDSO24
封装: QSOP-24
文件页数: 7/9页
文件大小: 229K
代理商: ZIF600
6
ZIF600
Fig.6 Control signal timing diagram for ZIF600 receiving data
Previous Signal
BS1
"A" -> Frame
Info
Sync 2
Block 0
Block 10
Next Signal
Off
Hold
Slow Track
Fast
Track
PLL Settle
Off
Signal
ZIF 600
Mode
VREF
PLLC
DSC1
DSC2
SRF
1.25v
0v
45mS
20mS
70mS
25mS
1·76 Sec.
VREF On
XTAL On
Synth. On
Demod. Off
Fast Track On
SRF=1600
Demod. On
Synth.On
Fast AFC On
Slow Track On
SRF=1600 or 3200
Demod. On
Synth.On
Slow AFC On
Hold Track
SRF=1600/3200
Demod. On
Synth.On
Hold AFC
SRF=1600
Demod. Off
Synth.On
Hold AFC
All
Off
All
Off
CONTROL BUS
The ZIF600 has its synthesiser and demodulator configured
by a three wire control bus (CLOCK, DATA, LE). The ZIF600
must have these commands applied to it before it can be used.
Each command must be complete. Data is clocked into the
ZIF600 on the rising edg of the clock. Data is latched into the
internal registers when ENABLE is high. Since the ENABLE pin
gives a direct load and also resets some circuits, there will be
a phase discontinuity if data is loaded after the synthesser has
settled. The bus clock does not need to run between messages
and to minimise interference to radio receiver circuits it is
recommended that the clock is stopped whenever it is not
needed. Fig. 7 shows the format of the control bus.
Fig.7 Control bus waveforms
Control bus timing (provisional)
th
ts
tpw
tse
tpe
20nS
20nS
50nS
20nS
50nS
CLOCK
DATA
LE
th
ts
tpw
tse
tpe
B15
B0
CLOCK
DATA
LE
ADD
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