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参数资料
| 型号： | ZIF600 |
| 厂商： | ZARLINK SEMICONDUCTOR INC |
| 元件分类： | 寻呼电路 |
| 英文描述： | Pager Synthesiser and 4FSK Demodulator |
| 中文描述： | TELECOM, PAGING DECODER, PDSO24 |
| 封装： | QSOP-24 |
| 文件页数： | 8/9页 |
| 文件大小： | 229K |
| 代理商： | ZIF600 |
7
ZIF600
PROGRAMMING FORMAT (PRELIMINARY)
Time Order First......
...Last
Bit No. (B)
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
ADD
Synthesiser
FCH "0"
"0"
System Set-up "0"
"0"
"0"
"0"
"0"
"0"
"0"
"0"
"0"
DMO RD5 RD4 RD3 RD2 RD1
"0"
"1"
Table 8. Programming format
Within each field parameters are ordered MSB first and
thenin descending order. Data is retained by ZIF600 until
VDDD is removed.
Name
FCH
Length
16 bit word
Meaning
Synthesiser programmable divider ratio
RD5 -> RD1
5 Bits
programming word to set crystal reference division ratio
DMO
1
Demodulator only operation. Set to "1" to power up only the reference oscillator and divider
with "PLLC" pin, generating demod. clock & leaving the remainder of PLL in power down.
Table 9. Control bus bit definitions
APPLICATIONS INFORMATION
By using constant current charge pumps the synthesiser
loop filter is purely passive. See Fig.8.
It is recommended that the primary filter is placed as close
to the synthesiser circuit as possible to minimise interference
caused by charge pump current pulses. The high frequency
clean-up filter, if needed at all, can be placed nearer the VCO
as required for board layout.
Suggested component values for
kHz comparison
frequency with a 5MHz/volt VCO are:
R1 = 15k
C1 = 220nF
CP = 18nF
RF = 47k
CF = 1.8nF
CP
R1
C1
CF
To VCO
PDOUT
PRELIMINARY
FILTER
RF
Fig.8 Typical synthesiser loop filter
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