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参数资料
| 型号： | ZIF600 |
| 厂商： | ZARLINK SEMICONDUCTOR INC |
| 元件分类： | 寻呼电路 |
| 英文描述： | Pager Synthesiser and 4FSK Demodulator |
| 中文描述： | TELECOM, PAGING DECODER, PDSO24 |
| 封装： | QSOP-24 |
| 文件页数： | 5/9页 |
| 文件大小： | 229K |
| 代理商： | ZIF600 |
4
ZIF600
SYNTHESISER
The Synthesiser divides the VCOFIN frequency by the 16-
bit number FCH programmed from the serial bus and then the
phase detector compares the result with the comparison
frequency signal to generate correction pulses. The division
ratio range is 4,032 to 65,535.
An embedded two modulus prescaler is used to minimise
power consumption but its programming is arranged to be
transparent to the user.
By using a digital phase and frequency detector the loop will
pull in over an unlimited range and then by using a reset signal
fed back from the output current drivers any delays in the
output path do not give a dead band in the phase response.
The charge pump currents are set by internal biasing. The
current level fixed by the circuit has been selected to give
minimum loop disturbance from external interference, while
also not taking excessive current from the supply line. It is
expected that adequate high frequency decoupling will be
provided on the power supplies to eliminate any significant
noise.
Powering up the synthesiser requires that VREF, IBIAS
and PLLC have been turned on for an adequate time before the
synthesiser is required to be functioning.
As the demodulator takes its clock from the synthesiser
reference divider, the synthesiser reference oscillator and
divider circuits must be on and have settled before the
demodulator is turned on.
Setting the "DMO" bit in the control bus allows the main
parts of the synthesiser to be kept in a low power mode with
only the reference oscillator and reference divider operating,
when PLLC is high. This effectively allows the demodulator to
be used standalone with its required clock being provided by
the reference oscillator/divider.
Fig.4 Basic block diagram of synthesiser
"DMO" bit
0
1
0
1
PLLC
0
0
1
1
Synthesiser Mode
Synthesiser off
Synthesiser off
Synthesiser on
Reference oscillator and divider on, remainder of synthesiser circuitry off
Table 4. Synthesiser mode control
16 BIT DIVIDER
CHARGE
PUMP
PDOUT
PHASE
DETECTOR
FCH FROM BUS (16 bit)
RESET
COMPARISON FREQUENCY
(FROM REFERENCE DIVIDER)
VCOFIN
UP
Φ
DOWN
Φ
Fig.3 Reference divider configuration
÷
8
÷
8/9
RD1
÷
4/5
RD2
÷
2/4
RD3
÷
1/2/3/4
RD4
RD5
CRYSTAL FREQUENCY
12·8 or 14·4 MHz
COMPARISON
FREQUENCY
200 kHz CLOCK TO DEMODULATOR
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