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参数资料
| 型号： | ZIF600 |
| 厂商： | ZARLINK SEMICONDUCTOR INC |
| 元件分类： | 寻呼电路 |
| 英文描述： | Pager Synthesiser and 4FSK Demodulator |
| 中文描述： | TELECOM, PAGING DECODER, PDSO24 |
| 封装： | QSOP-24 |
| 文件页数： | 3/9页 |
| 文件大小： | 229K |
| 代理商： | ZIF600 |
2
ZIF600
TARGET ELECTRICAL CHARACTERISTICS
These characteristics are guaranteed over the following conditions (unless otherwise stated):
VDDD, VDDA = 2.7 TO 3.3V, VDD1 = 0.95V to 1.6V (connected to REFOSCB via ext. resistor) and T
amb
= —20 to + 70
°
C
Characteristic
Min.
Typ.
Max.
Units
Conditions
Supply current at VDDD,VDDA = 3V
-
1
-
mA
Synthesiser locked and
demodulator active. VDD1
connected to REFOSCB
via external resistor.
Supply current at VDD1 = 1.4V
-
350
-
μ
A
VREF bias voltage input range
1.15
1.25
1.31
V
Logic input HIGH, pins DATA, CLOCK,
LE, DSC1, DSC2, PLLC, SRF, RXI, RXQ
VDD - 0.3
-
VDD + 0.3
V
Logic input HIGH, pins DATA, CLOCK,
LE, DSC1, DSC2, PLLC, SRF, RXI, RXQ
VSS - 0.3
-
VSS + 0.3
V
Input capacitance (signal pins)
-
-
10
pF
Pin voltage: VSS to VDD
Input leakage (signal pins)
-
-
1
μ
A
Pin voltage: VSS to VDD
Control bus CLOCK frequency
0
-
10
MHz
Synthesiser charge pump output
leakage, pin PDOUT
-
50
-
nA
Pin voltage:
VSS to VDD
Synthesiser charge pump output
current, pin PDOUT
160
200
240
μ
A
Pin VDD/2
Charge pump output compliance
range, pin PDOUT
VSS + 0.4
-
VDD — 0.4
V
Current within 10% of its
value at VDD/2
Main synthesiser input frequency on
VCOFIN
50
-
330
MHz
VCOFIN input level
300
-
1000
mV
pk - pk
Reference Frequency Crystal
-
12.8
14.4
-
MHz
Pins REFOSC and
REFOSCB
Logic output HIGH, pins DATA0,
DATA1
VDD — 0.3
-
VDD
V
Output current, IoH =
100
μ
A
Logic output LOW, pins DATA0,
DATA1
VSS
-
VSS — 0.3
V
Output current, IoL =
100
μ
A.
Trim DAC output voltage, pin DACOUT
0
-
2.375
V
Not tested Output current
100nA VREF = 1.25V
RXI, RXQ pull-up current
1.5
-
-
μ
A
VDD — 0.3V
RXI, RXQ pull-up current
-
-
40
μ
A
VSS + 0.3V
Input leakage (signal) pins with
pull-downs
-
-
3
μ
A
Pin voltage: VSS to VDD
pins include SRF, PLLC
DSC1, DSC2
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