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参数资料
| 型号： | ZL30402/QCC1 |
| 厂商： | ZARLINK SEMICONDUCTOR INC |
| 元件分类： | 数字传输电路 |
| 英文描述： | ATM/SONET/SDH SUPPORT CIRCUIT, PQFP80 |
| 封装： | 14 X 14 MM, 1.40 MM HEIGHT, MS-026BEC, LQFP-80 |
| 文件页数： | 6/44页 |
| 文件大小： | 472K |
| 代理商： | ZL30402/QCC1 |
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ZL30402
Data Sheet
14
Zarlink Semiconductor Inc.
Figure 4 - C19o, C155o, C34/C44 Clock Generation Options
All clocks and frame pulses except the C155 are output with CMOS logic levels. The C155 clock (155.52MHz) is
output in a standard LVDS format.
2.5
Output Clocks Phase Adjustment
The ZL30402 provides three control registers dedicated to programming the output clock phase offset. Clocks
C16o, C8o, C4o and C2o and frame pulses F16o, F8o, F0o are derived from 16.384 MHz and can be jointly shifted
with respect to an active reference clock by up to 125 s with a step size of 61 ns. The required phase shift of
clocks is programmable by writing to the Phase Offset Register 2 ("Table 8") and to the Phase Offset Register 1
("Table 9"). The C1.5o clock can be shifted as well in step sizes of 81ns by programming C1.5POA bits in Control
Register 3 ("Table 11").
The coarse phase adjustment is augmented with a very fine phase offset control on the order of 477 ps per step.
This fine adjustment is programmable by writing to the Fine Phase Offset Register (Table 15 "Fine Phase Offset
Register (R/W)"). The offset moves all clocks and frame pulses generated by ZL30402 including C155 clock.
2.6
Control State Machine
2.6.1
Clock Modes
Any Network Element that operates in a synchronous network must support three Clock Modes: Free-run, Normal
(Locked) and Holdover. These clock modes determine behavior of a Network Element to the unforeseen changes in
the network synchronization hierarchy. Requirements for Clock Modes are defined in the international standards
e.g.: G.813, GR-1244-CORE and GR-253-CORE and they are very strictly enforced by network operators. The
ZL30402 supports all clock modes and each of these modes have a corresponding state in the Control State
Machine.
2.6.2
ZL30402 State Machine
The ZL30402 Control State Machine is a complex combination of many internal states supporting the three
mandatory clock modes. The simplified version of this state machine is shown in Figure 5 and it includes the
mandatory states: Free-run, Normal and Holdover. These three states are complemented by two additional states:
Reset and Auto Holdover, which are critical to the ZL30402 operation under the changing external conditions.
C155 Output
C19o Output
C34/44 Output
E3DS3/OC3
0
1
0
1
01
155.52
HIZ
19.44
Dejittered
19.44
11.184
44.736
8.592
34.368
E3/DS3
0
1
E3DS3/OC3
C155 Output
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| ZL30402/QCG1 | ATM/SONET/SDH SUPPORT CIRCUIT, PQFP80 |
| ZL50112GAG2 | SPECIALTY TELECOM CIRCUIT, PBGA552 |
| ZL50112GAG | SPECIALTY TELECOM CIRCUIT, PBGA552 |
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相关代理商/技术参数 |
参数描述 |
|---|---|
| ZL30402QCG1 | 制造商:Microsemi Corporation 功能描述:PB FREE SONET / SDH NETWORK ELEMENT PLL - Trays 制造商:MICROSEMI CONSUMER MEDICAL PRODUCT GROUP 功能描述:IC NETWORK PLL SONET/SDH 80LQFP 制造商:Microsemi Corporation 功能描述:IC NETWORK PLL SONET/SDH 80LQFP |
| ZL30406 | 制造商:ZARLINK 制造商全称:Zarlink Semiconductor Inc 功能描述:SONET/SDH Clock Multiplier PLL |
| ZL30406_06 | 制造商:ZARLINK 制造商全称:Zarlink Semiconductor Inc 功能描述:SONET/SDH Clock Multiplier PLL |
| ZL30406QGC | 制造商:Zarlink Semiconductor Inc 功能描述:PLL CLOCK MLTPLR SGL UP TO 19.44MHZ 64TQFP - Trays |
| ZL30406QGC1 | 制造商:ZARLINK 制造商全称:Zarlink Semiconductor Inc 功能描述:SONET/SDH Clock Multiplier PLL |
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