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Zarlink Semiconductor Inc.
Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.
Copyright 2003-2009, Zarlink Semiconductor Inc. All Rights Reserved.
Features
General
Circuit Emulation Services over Packet (CESoP)
transport for MPLS, IP and Ethernet networks
On chip timing & synchronization recovery across
a packet network
Grooming capability for Nx64 Kbps trunking
Circuit Emulation Services
Supports ITU-T Recommendation Y.1413 and
Y.1453
Supports IETF RFC4553 and RFC5086
Supports MEF8 and MFA 8.0.0
Structured, synchronous CESoP with clock
recovery
Unstructured, asynchronous CESoP, with integral
per stream clock recovery
TDM Interfaces
Up to 32 T1/E1, 8 J2, or 2 T3/E3 ports
H.110, H-MVIP, ST-BUS backplanes
Up to 1024 bi-directional 64 Kbps channels
Direct connection to LIUs, framers, backplanes
Dual reference Stratum 4 and 4E DPLL for
synchronous operation
Network Interfaces
Up to 3 x 100 Mbps MII Fast Ethernet or Dual
Redundant 1000 Mbps GMII/TBI Ethernet
Interfaces
System Interfaces
Flexible 32 bit host CPU interface (Motorola
PowerQUICC compatible)
On-chip packet memory for self-contained
operation, with buffer depths of over 16 ms
Up to 8 Mbytes of off-chip packet memory,
supporting buffer depths of over 128 ms
March 2009
Ordering Information
ZL50110GAG
552 PBGA
Trays, Bake & Drypack
ZL50111GAG
552 PBGA
Trays, Bake & Drypack
ZL50112GAG
552 PBGA
Trays, Bake & Drypack
ZL50114GAG
552 PBGA
Trays, Bake & Drypack
ZL50110GAG2
552 PBGA** Trays, Bake & Drypack
ZL50111GAG2
552 PBGA** Trays, Bake & Drypack
ZL50112GAG2
552 PBGA** Trays, Bake & Drypack
ZL50114GAG2
552 PBGA** Trays, Bake & Drypack
**Pb Fee Tin Silver/Copper
-40°C to +85°C
ZL50110/11/12/14
128, 256, 512 and 1024 Channel CESoP
Processors
Data Sheet
Figure 1 - ZL50111 High Level Overview
On C h ip P a c k e t Me m o ry
(J itte r B u ffe r C o m pens atio n fo r 16-128 m s of P a c k et D e la y V a riation)
D u al R e fe renc e
DP L L
H o st P ro c e sso r
In te rfa c e
E x te rn a l M e m o ry
In te rfac e (optio n a l)
H
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,
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ST
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M
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32-bit M o to ro la c o m p atib le P Q II
M u lti-P rotoc ol
P a cke t
P roc es s ing
En g in e
P W , RT P , UDP ,
IP v 4 , IP v 6 , M P L S ,
ECID , VL AN, U s e r
D e fined, O thers
Trip le
P a cke t
In te rfa c e
MA C
(M II, G M II, T B I)
TD M
In te rfa c e
(L IU , Fram er, B a c k pla ne)
Pe r Po rt DC O fo r
Clo c k Re c o v e ry
Z B T -SRAM
(0 - 8 M b y tes )
32
T
1
/E
1
,
8
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