参数资料
型号: ZL50232GD
厂商: ZARLINK SEMICONDUCTOR INC
元件分类: 数字传输电路
英文描述: DATACOM, ISDN ECHO CANCELLER, PBGA208
封装: 17 X 17 MM, 1.30 MM HEIGHT, LBGA-208
文件页数: 1/41页
文件大小: 809K
代理商: ZL50232GD
1
Zarlink Semiconductor Inc.
Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.
Copyright 2003, Zarlink Semiconductor Inc. All Rights Reserved.
Features
Independent multiple channels of echo
cancellation; from 32 channels of 64 ms to 16
channels of 128 ms with the ability to mix
channels at 128 ms or 64 ms in any combination
Independent Power Down mode for each group
of 2 channels for power management
Fully compliant to ITU-T G.165, G.168 (2000) and
(2002) specifications
Passed all AT&T voice quality tests for carrier
grade echo canceller.
Compatible to ST-BUS and GCI interface at
2 Mbps serial PCM
PCM coding,
/A-Law ITU-T G.711 or sign
magnitude
Per channel Fax/Modem G.164 2100Hz or G.165
2100Hz phase reversal Tone Disable
Per channel echo canceller parameters control
Transparent data transfer and mute
Fast reconvergence on echo path changes
Fully programmable convergence speeds
Patented Advanced Non-Linear Processor with
high quality subjective performance
Protection against narrow band signal
divergence and instability in high echo
environments
+9 dB to -12 dB level adjusters (3 dB steps) at all
signal ports
Offset nulling of all PCM channels
10 MHz or 20 MHz master clock operation
3.3 V pads and 1.8 V Logic core operation with
5 V tolerant inputs
IEEE-1149.1 (JTAG) Test Access Port
Applications
Voice over IP network gateways
Voice over ATM, Frame Relay
T1/E1/J1 multichannel echo cancellation
Wireless base stations
Echo Canceller pools
DCME, satellite and multiplexer system
December 2003
Ordering Information
ZL50232QC
100-Pin LQFP
ZL50232GD
208-Ball LBGA
-40
°C to +85°C
ZL50232
32 Channel Voice Echo Canceller
Data Sheet
Figure 1 - ZL50232 Device Overview
RESET
Rout
IC0
Sout
DS CS R/W A10-A0 DTA D7-D0
Echo Canceller Pool
VSS
VDD1 (3.3V)
TDI TDO TCK TRST
TMS
Rin
IRQ
C4i
F0i
MCLK
ODE
Sin
Fsel
Test Port
Microprocessor Interface
Timing
Unit
Serial
to
Parallel
to
Serial
PLL
Group 0
ECA/ECB
Group 4
ECA/ECB
Group 8
ECA/ECB
Group 12
ECA/ECB
Group 1
ECA/ECB
Group 5
ECA/ECB
Group 9
ECA/ECB
Group 13
ECA/ECB
Group 2
ECA/ECB
Group 6
ECA/ECB
Group 10
ECA/ECB
Group 14
ECA/ECB
Group 3
ECA/ECB
Group 7
ECA/ECB
Group 11
ECA/ECB
Group 15
ECA/ECB
Note:
Refer to Figure 4
for Echo Canceller
block diagram
VDD2 (1.8 V)
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