- 您现在的位置：买卖IC网 > PDF目录300164 > ZL50232GD (ZARLINK SEMICONDUCTOR INC) DATACOM, ISDN ECHO CANCELLER, PBGA208 PDF资料下载
参数资料
| 型号： | ZL50232GD |
| 厂商： | ZARLINK SEMICONDUCTOR INC |
| 元件分类： | 数字传输电路 |
| 英文描述： | DATACOM, ISDN ECHO CANCELLER, PBGA208 |
| 封装： | 17 X 17 MM, 1.30 MM HEIGHT, LBGA-208 |
| 文件页数： | 11/41页 |
| 文件大小： | 809K |
| 代理商： | ZL50232GD |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页当前第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页
ZL50232
Data Sheet
19
Zarlink Semiconductor Inc.
6.7
Interrupts
The ZL50232 provides an interrupt pin (IRQ) to indicate to the HOST processor when a G.164 or G.165 Tone
Disable is detected and released.
Although the ZL50232 may be configured to react automatically to tone disable status on any input PCM voice
channels, the user may want for the external HOST processor to respond to Tone Disable information in an
appropriate application-specific manner.
Each echo canceller will generate an interrupt when a Tone Disable occurs and will generate another interrupt
when a Tone Disable releases.
Upon receiving an IRQ, the HOST CPU should read the Interrupt FIFO Register. This register is a FIFO memory
containing the channel number of the echo canceller that has generated the interrupt.
All pending interrupts from any of the echo cancellers and their associated input channel number are stored in this
FIFO memory. The IRQ always returns high after a read access to the Interrupt FIFO Register. The IRQ pin will
toggle low for each pending interrupt.
After the HOST CPU has received the channel number of the interrupt source, the corresponding per channel
Status Register can be read from internal memory to determine the cause of the interrupt (see Table 3 for address
mapping of Status register). The TD bit indicates the presence of a Tone Disable.
The MIRQ bit 5 in the Main Control Register 0 masks interrupts from the ZL50232. To provide more flexibility, the
MTDBI (bit-4) and MTDAI (bit-3) bits in the Main Control Register<15:0> allow Tone Disable to be masked or
unmasked from generating an interrupt on a per channel basis. Refer to the Registers Description section.
7.0
JTAG Support
The ZL50232 JTAG interface conforms to the Boundary-Scan standard IEEE1149.1. This standard specifies a
design-for-testability technique called Boundary-Scan test (BST). The operation of the Boundary Scan circuitry is
controlled by an Test Access Port (TAP) controller. JTAG inputs are 3.3 V compliant only.
7.1
Test Access Port (TAP)
The TAP provides access to many test functions of the ZL50232. It consists of four input pins and one output pin.
The following pins are found on the TAP.
Test Clock Input (TCK)
The TCK provides the clock for the test logic. The TCK does not interfere with any on-chip clock and thus
remains independent. The TCK permits shifting of test data into or out of the Boundary-Scan register cells
concurrent with the operation of the device and without interfering with the on-chip logic.
Test Mode Select Input (TMS)
The logic signals received at the TMS input are interpreted by the TAP Controller to control the test operations.
The TMS signals are sampled at the rising edge of the TCK pulse. This pin is internally pulled to VDD1 when it is
not driven from an external source.
Test Data Input (TDI)
Serial input data applied to this port is fed either into the instruction register or into a test data register,
depending on the sequence previously applied to the TMS input. Both registers are described in a subsequent
section. The received input data is sampled at the rising edge of TCK pulses. This pin is internally pulled to
VDD1 when it is not driven from an external source.
Test Data Output (TDO)
Depending on the sequence previously applied to the TMS input, the contents of either the instruction register
or data register are serially shifted out towards the TDO. The data from the TDO is clocked on the falling edge
of the TCK pulses. When no data is shifted through the Boundary Scan cells, the TDO driver is set to a high
impedance state.
相关PDF资料 |
PDF描述 |
|---|---|
| ZL50233/GDG | DATACOM, ISDN ECHO CANCELLER, PBGA208 |
| ZL50408GDC | DATACOM, LAN SWITCHING CIRCUIT, PBGA208 |
| ZL50408GDG2 | DATACOM, LAN SWITCHING CIRCUIT, PBGA208 |
| ZL50418GKG2 | DATACOM, LAN SWITCHING CIRCUIT, PBGA553 |
| ZL50418/GKC | DATACOM, LAN SWITCHING CIRCUIT, PBGA553 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| ZL50232GDC | 制造商:ZARLINK 制造商全称:Zarlink Semiconductor Inc 功能描述:32 Channel Voice Echo Canceller |
| ZL50232GDG2 | 制造商:Microsemi Corporation 功能描述: 制造商:Microsemi Corporation 功能描述:ECHO CANCELLER CHIP 32CH G.165/G.168/G.711 W/ TONE DETECTION - Trays 制造商:MICROSEMI CONSUMER MEDICAL PRODUCT GROUP 功能描述:IC VOICE ECHO CANCELLER 208LBGA 制造商:Microsemi Corporation 功能描述:IC VOICE ECHO CANCELLER 208LBGA |
| ZL50232QCC | 制造商:ZARLINK 制造商全称:Zarlink Semiconductor Inc 功能描述:32 Channel Voice Echo Canceller |
| ZL50232QCC1 | 制造商:ZARLINK 制造商全称:Zarlink Semiconductor Inc 功能描述:32 Channel Voice Echo Canceller |
| ZL50232QCG1 | 制造商:Microsemi Corporation 功能描述:ECHO CANCELLER CHIP 32CH G.165/G.168/G.711 W/ TONE DETECTION - Trays 制造商:Microsemi Corporation 功能描述:PB FREE 32 CHANNEL VOICE ECHO CANCELLER |
发布紧急采购，3分钟左右您将得到回复。