参数资料
型号: ZL50232GD
厂商: ZARLINK SEMICONDUCTOR INC
元件分类: 数字传输电路
英文描述: DATACOM, ISDN ECHO CANCELLER, PBGA208
封装: 17 X 17 MM, 1.30 MM HEIGHT, LBGA-208
文件页数: 26/41页
文件大小: 809K
代理商: ZL50232GD
ZL50232
Data Sheet
32
Zarlink Semiconductor Inc.
Power-up
N/A
ECA: Rin Peak Detect Register 2 (RP)
Read Address:
0Dhex + Base Address
ECB: Rin Peak Detect Register 2 (RP)
Read Address:
2Dhex + Base Address
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
RP15
RP14
RP13
RP12
RP11
RP10
RP9
RP8
Power-up
N/A
ECA: Rin Peak Detect Register 1 (RP)
Read Address:
0Chex + Base Address
ECB: Rin Peak Detect Register 1 (RP)
Read Address:
2Chex + Base Address
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
RP7
RP6
RP5
RP4
RP3
RP2
RP1
RP0
Functional Description of Register Bits
These peak detector registers allow the user to monitor the receive in (Rin) peak signal level. The information
is in 16-bit 2’s complement linear coded format presented in two 8 bit registers for each echo canceller. The
high byte is in Register 2 and the low byte is in Register 1.
Power-up
N/A
ECA: Sin Peak Detect Register 2 (SP)
Read Address:
0Fhex + Base Address
ECB: Sin Peak Detect Register 2 (SP)
Read Address:
2Fhex + Base Address
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
SP15
SP14
SP13
SP12
SP11
SP10
SP9
SP8
Power-up
N/A
ECA: Sin Peak Detect Register 1 (SP)
Read Address:
0Ehex + Base Address
ECB: Sin Peak Detect Register 1 (SP)
Read Address:
2Ehex + Base Address
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
SP7
SP6
SP5
SP4
SP3
SP2
SP1
SP0
Functional Description of Register Bits
These peak detector registers allow the user to monitor the send in (Sin) peak signal level. The information is in
16-bit 2’s complement linear coded format presented in two 8 bit registers for each echo canceller. The high
byte is in Register 2 and the low byte is in Register 1.
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