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参数资料
| 型号： | ZL50232GD |
| 厂商： | ZARLINK SEMICONDUCTOR INC |
| 元件分类： | 数字传输电路 |
| 英文描述： | DATACOM, ISDN ECHO CANCELLER, PBGA208 |
| 封装： | 17 X 17 MM, 1.30 MM HEIGHT, LBGA-208 |
| 文件页数： | 38/41页 |
| 文件大小： | 809K |
| 代理商： | ZL50232GD |
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ZL50232
Data Sheet
6
Zarlink Semiconductor Inc.
1.0
Device Overview
The ZL50232 architecture contains 32 echo cancellers divided into 16 groups. Each group has two echo cancellers,
Echo Canceller A and Echo Canceller B. Each group can be configured in Normal, Extended Delay or
Back-to-Back configurations. In Normal configuration, a group of echo cancellers provides two channels of 64 ms
echo cancellation, which run independently on different channels. In Extended Delay configuration, a group of
echo cancellers achieves 128 ms of echo cancellation by cascading the two echo cancellers (A & B). In
Back-to-Back configuration, the two echo cancellers from the same group are positioned to cancel echo coming
from both directions in a single channel, providing full-duplex 64 ms echo cancellation.
Fsel
H2
92
Frequency select (Input). This input selects the Master Clock
frequency operation. When Fsel pin is low, nominal 19.2 MHz
Master Clock input must be applied. When Fsel pin is high,
nominal 9.6 MHz Master Clock input must be applied.
PLLVss1
PLLVss2
K3
97, 95
PLL Ground. Must be connected to VSS
PLLVDD K4
96
PLL Power Supply. Must be connected to VDD2 = 1.8 V
TMS
M2
1
Test Mode Select (3.3 V Input). JTAG signal that controls the
state transitions of the TAP controller. This pin is pulled high by
an internal pull-up when not driven.
TDI
M1
2
Test Serial Data In (3.3 V Input). JTAG serial test instructions
and data are shifted in on this pin. This pin is pulled high by an
internal pull-up when not driven.
TDO
N1
3
Test Serial Data Out (Output). JTAG serial data is output on this
pin on the falling edge of TCK. This pin is held in high impedance
state when JTAG scan is not enabled.
TCK
P1
4
Test Clock (3.3 V Input). Provides the clock to the JTAG test
logic.
TRST
N2
6
Test Reset (3.3 V Input). Asynchronously initializes the JTAG
TAP controller by putting it in the Test-Logic-Reset state. This pin
should be pulsed low on power-up or held low, to ensure that the
ZL50232 is in the normal functional mode. This pin is pulled by
an internal pull-down when not driven.
RESET R3
8
Device Reset (Schmitt Trigger Input). An active low resets the
device and puts the ZL50232 into a low-power stand-by mode.
When the RESET pin is returned to logic high and a clock is
applied to the MCLK pin, the device will automatically execute
initialization routines, which preset all the Main Control and
Status Registers to their default power-up values.
Pin Description (continued)
PIN
Name
PIN #
Description
208-Ball LBGA
100 PIN
LQFP
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相关代理商/技术参数 |
参数描述 |
|---|---|
| ZL50232GDC | 制造商:ZARLINK 制造商全称:Zarlink Semiconductor Inc 功能描述:32 Channel Voice Echo Canceller |
| ZL50232GDG2 | 制造商:Microsemi Corporation 功能描述: 制造商:Microsemi Corporation 功能描述:ECHO CANCELLER CHIP 32CH G.165/G.168/G.711 W/ TONE DETECTION - Trays 制造商:MICROSEMI CONSUMER MEDICAL PRODUCT GROUP 功能描述:IC VOICE ECHO CANCELLER 208LBGA 制造商:Microsemi Corporation 功能描述:IC VOICE ECHO CANCELLER 208LBGA |
| ZL50232QCC | 制造商:ZARLINK 制造商全称:Zarlink Semiconductor Inc 功能描述:32 Channel Voice Echo Canceller |
| ZL50232QCC1 | 制造商:ZARLINK 制造商全称:Zarlink Semiconductor Inc 功能描述:32 Channel Voice Echo Canceller |
| ZL50232QCG1 | 制造商:Microsemi Corporation 功能描述:ECHO CANCELLER CHIP 32CH G.165/G.168/G.711 W/ TONE DETECTION - Trays 制造商:Microsemi Corporation 功能描述:PB FREE 32 CHANNEL VOICE ECHO CANCELLER |
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