参数资料
型号: ZL50232GD
厂商: ZARLINK SEMICONDUCTOR INC
元件分类: 数字传输电路
英文描述: DATACOM, ISDN ECHO CANCELLER, PBGA208
封装: 17 X 17 MM, 1.30 MM HEIGHT, LBGA-208
文件页数: 39/41页
文件大小: 809K
代理商: ZL50232GD
ZL50232
Data Sheet
7
Zarlink Semiconductor Inc.
Each echo canceller contains the following main elements (see Figure 4).
Adaptive Filter for estimating the echo channel
Subtractor for cancelling the echo
Double-Talk detector for disabling the filter adaptation during periods of double-talk
Path Change detector for fast reconvergence on major echo path changes
Instability Detector to combat instability in very low ERL environments
Patented Advanced Non-Linear Processor for suppression of residual echo, with comfort noise injection
Disable Tone Detectors for detecting valid disable tones at send and receive path inputs
Narrow-Band Detector for preventing Adaptive Filter divergence from narrow-band signals
Offset Null filters for removing the DC component in PCM channels
+9 to -12 dB level adjusters at all signal ports
Parallel controller interface compatible with Motorola microcontrollers
PCM encoder/decoder compatible with
/A-Law ITU-T G.711 or Sign-Magnitude coding
Each echo canceller in the ZL50232 has four functional states: Mute, Bypass, Disable Adaptation and Enable
Adaptation. These are explained in the section entitled Echo Canceller Functional States.
Figure 4 - Functional Block Diagram
1.1
Adaptive Filter
The adaptive filter adapts to the echo path and generates an estimate of the echo signal. This echo estimate is then
subtracted from Sin. For each group of echo cancellers, the adaptive filter is a 1024 tap FIR adaptive filter which is
divided into two sections. Each section contains 512 taps providing 64 ms of echo estimation. In Normal
configuration, the first section is dedicated to channel A and the second section to channel B. In Extended Delay
configuration, both sections are cascaded to provide 128 ms of echo estimation in channel A. In Back-to Back
configuration, the first section is used in the receive direction and the second section is used in the transmit
direction for the same channel.
Σ
Non-Linear
Processor
Offset
Null
Linear/
/A-Law
Microprocessor
Interface
Double - Talk
Detector
Co
nt
ro
l
Narrow-Band
Detector
/A-Law/
Linear
Offset
Null
Echo Canceller (N), where 0 < N < 31
Sout
Rin
Sin
Rout
-
Programmable Bypass
(channel N)
ST-BUS
PORT2
PORT1
MuteR
MuteS
+9 to -12 dB
Level Adjust
Linear/
/A-Law
+9 to -12 dB
Level Adjust
+9 to -12 dB
Level Adjust
/A-Law/
Linear
+9 to -12 dB
Level Adjust
Ada
p
tive
Fi
lter
Disable Tone
Detector
Disable Tone
Detector
Path Change
Instability
Detector
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