参数资料
型号: ZL50232GD
厂商: ZARLINK SEMICONDUCTOR INC
元件分类: 数字传输电路
英文描述: DATACOM, ISDN ECHO CANCELLER, PBGA208
封装: 17 X 17 MM, 1.30 MM HEIGHT, LBGA-208
文件页数: 6/41页
文件大小: 809K
代理商: ZL50232GD
ZL50232
Data Sheet
14
Zarlink Semiconductor Inc.
In Back-to-Back configuration, writing a “1” into the MuteR bit of Echo Canceller A, Control Register 2, causes
quiet code to be transmitted on Rout. Writing a “1” into the MuteS bit of Echo Canceller A, Control Register 2,
causes quiet code to be transmitted on Sout.
In Extended Delay and in Back-to-Back configurations, MuteR and MuteS bits of Echo Canceller B must always be
“0”. Refer to Figure 4 and to Control Register 2 for bit description.
3.2
Bypass
The Bypass state directly transfers PCM codes from Rin to Rout and from Sin to Sout. When Bypass state is
selected, the Adaptive Filter coefficients are reset to zero. Bypass state must be selected for at least one frame
(125
s) in order to properly clear the filter.
3.3
Disable Adaptation
When the Disable Adaptation state is selected, the Adaptive Filter coefficients are frozen at their current value. The
adaptation process is halted, however, the echo canceller continues to cancel echo.
3.4
Enable Adaptation
In Enable Adaptation state, the Adaptive Filter coefficients are continually updated. This allows the echo canceller
to model the echo return path characteristics in order to cancel echo. This is the normal operating state.
The echo canceller functions are selected in Control Register 1 and Control Register 2 through four control bits:
MuteS, MuteR, Bypass and AdaptDis. Refer to the Registers Description for details.
4.0
ZL50232 Throughput Delay
The throughput delay of the ZL50232 varies according to the device configuration. For all device configurations, Rin
to Rout has a delay of two frames and Sin to Sout has a delay of three frames. In Bypass state, the Rin to Rout and
Sin to Sout paths have a delay of two frames.
5.0
Serial PCM I/O channels
There are two sets of TDM I/O streams, each with channels numbered from 0 to 31. One set of input streams is for
Receive (Rin) channels, and the other set of input streams is for Send (Sin) channels. Likewise, one set of output
streams is for Rout PCM channels, and the other set is for Sout channels. See Figure 9 for channel allocation.
The arrangement and connection of PCM channels to each echo canceller is a 2 port I/O configuration for each set
of PCM Send and Receive channels, as illustrated in Figure 4.
5.1
Serial Data Interface Timing
The ZL50232 provides ST-BUS and GCI interface timing. The Serial Interface clock frequency, C4i, is 4.096 MHz.
The input and output data rate of the ST-BUS and GCI bus is 2.048 Mbps.
The 8 KHz input frame pulse can be in either ST-BUS or GCI format. The ZL50232 automatically detects the
presence of an input frame pulse and identifies it as either ST-BUS or GCI. In ST-BUS format, every second falling
edge of the C4i clock marks a bit boundary, and the data is clocked in on the rising edge of C4i, three quarters of
the way into the bit cell (See Figure 12). In GCI format, every second rising edge of the C4i clock marks the bit
boundary, and data is clocked in on the second falling edge of C4i, half the way into the bit cell (see Figure 13).
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