参数资料
型号: ZL50232GD
厂商: ZARLINK SEMICONDUCTOR INC
元件分类: 数字传输电路
英文描述: DATACOM, ISDN ECHO CANCELLER, PBGA208
封装: 17 X 17 MM, 1.30 MM HEIGHT, LBGA-208
文件页数: 4/41页
文件大小: 809K
代理商: ZL50232GD
ZL50232
Data Sheet
12
Zarlink Semiconductor Inc.
2.0
Device Configuration
The ZL50232 architecture contains 32 echo cancellers divided into 16 groups. Each group has two echo cancellers
which can be individually controlled (Echo Canceller A (ECA) and Echo Canceller B (ECB)). They can be set in
three distinct configurations: Normal, Back-to-Back, and Extended Delay. See Figures 6, 7, and 8.
2.1
Normal Configuration
In Normal configuration, the two echo cancellers (Echo Canceller A and B) are positioned in parallel, as shown in
Figure 6, providing 64 milliseconds of echo cancellation in two channels simultaneously.
Figure 6 - Normal Device Configuration (64 ms)
2.2
Back-to-Back Configuration
In Back-to-Back configuration, the two echo cancellers from the same group are positioned to cancel echo coming
from both directions in a single channel providing full-duplex 64 ms echo cancellation. See Figure 7. This
configuration uses only one timeslot on PORT1 and PORT2 and the second timeslot normally associated with ECB
contains zero code. Back-to-Back configuration allows a no-glue interface for applications where bidirectional echo
cancellation is required.
Figure 7 - Back-to-Back Device Configuration (64 ms)
Rin
Rout
Sout
Sin
echo
path A
echo
path B
+
-
channel A
channel A
+
-
channel B
channel B
ECA
ECB
Adaptive
Filter (64 ms)
Adaptive
Filter (64 ms)
PORT1
PORT2
+
ECA
Sin
Sout
Rout
Rin
-
ECB
+
-
echo
path
Adaptive
Filter (64 ms)
Adaptive
Filter (64 ms)
PORT1
PORT2
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