参数资料
型号: ZL50232GD
厂商: ZARLINK SEMICONDUCTOR INC
元件分类: 数字传输电路
英文描述: DATACOM, ISDN ECHO CANCELLER, PBGA208
封装: 17 X 17 MM, 1.30 MM HEIGHT, LBGA-208
文件页数: 27/41页
文件大小: 809K
代理商: ZL50232GD
ZL50232
Data Sheet
33
Zarlink Semiconductor Inc.
Power-up
N/A
ECA: Error Peak Detect Register 2 (EP)
Read Address:
11hex + Base Address
ECB: Error Peak Detect Register 2 (EP)
Read Address:
31hex + Base Address
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
EP15
EP14
EP13
EP12
EP11
EP10
EP9
EP8
Power-up
N/A
ECA: Error Peak Detect Register 1 (EP)
Read Address:
10hex + Base Address
ECB: Error Peak Detect Register 1 (EP)
Read Address:
30hex + Base Address
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
EP7
EP6
EP5
EP4
EP3
EP2
EP1
EP0
Functional Description of Register Bits
These peak detector registers allow the user to monitor the error signal peak level. The information is in 16 bit
2’s complement linear coded format presented in two 8 bit registers for each echo canceller. The high byte is in
Register 2 and the low byte is in Register 1.
Power-up
48hex
ECA: Double-Talk Detection Threshold Register 2
R/W Address:
15hex + Base Address
ECB: Double-Talk Detection Threshold Register 2
R/W Address:
35hex + Base Address
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
DTDT15
DTDT14
DTDT13
DTDT12
DTDT11
DTDT10
DTDT9
DTDT8
Power-up
00hex
ECA: Double-Talk Detection Threshold Register 1
R/W Address:
14hex + Base Address
ECB: Double-Talk Detection Threshold Register 1
R/W Address:
34hex + Base Address
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
DTDT7
DTDT6
DTDT5
DTDT4
DTDT3
DTDT2
DTDT1
DTDT0
Functional Description of Register Bits
This register allows the user to program the level of Double-Talk Detection Threshold (DTDT). The 16 bit 2’s
complement linear value defaults to 4800hex= 0.5625 or -5 dB. The maximum value is 7FFFhex = 0.9999 or
0 dB. The high byte is in Register 2 and the low byte is in Register 1.
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