参数资料
型号: ZL50232GD
厂商: ZARLINK SEMICONDUCTOR INC
元件分类: 数字传输电路
英文描述: DATACOM, ISDN ECHO CANCELLER, PBGA208
封装: 17 X 17 MM, 1.30 MM HEIGHT, LBGA-208
文件页数: 5/41页
文件大小: 809K
代理商: ZL50232GD
ZL50232
Data Sheet
13
Zarlink Semiconductor Inc.
Back-to-Back configuration is selected by writing a “1” into the BBM bit of Control Register 1 for both Echo
Canceller A and Echo Canceller B for a given group of echo canceller. Table 4 shows the 16 groups of 2 cancellers
that can be configured into Back-to-Back.
Examples of Back-to-Back configuration include positioning one group of echo cancellers between a codec and a
transmission device or between two codecs for echo control on analog trunks.
2.3
Extended Delay Configuration
In this configuration, the two echo cancellers from the same group are internally cascaded into one 128
milliseconds echo canceller. See Figure 8. This configuration uses only one timeslot on PORT1 and PORT2 and
the second timeslot normally associated with ECB contains quiet code.
Figure 8 - Extended Delay Configuration (128 ms)
Extended Delay configuration is selected by writing a “1” into the ExtDl bit in Echo Canceller A, Control Register 1.
For a given group, only Echo Canceller A, Control Register 1, has the ExtDl bit. For Echo Canceller B Control
Register 1, Bit 0 must always be set to zero.
Table 4 shows the 16 groups of 2 cancellers that can each be configured into 64 ms or 128 ms echo tail capacity.
3.0
Echo Canceller Functional States
Each echo canceller has four functional states: Mute, Bypass, Disable Adaptation and Enable Adaptation.
3.1
Mute
In Normal and in Extended Delay configurations, writing a “1” into the MuteR bit replaces Rin with quiet code which
is applied to both the Adaptive Filter and Rout. Writing a “1” into the MuteS bit replaces the Sout PCM data with
quiet code.
LINEAR
16 bits
2’s
complement
SIGN/
MAGNITUDE
-Law
A-Law
CCITT (G.711)
-Law
A-Law
+Zero
(quiet code)
0000hex
80hex
FFhex
D5hex
Table 2 - Quiet PCM Code Assignment
+
-
channel A
ECA
Sin
Sout
Rout
Rin
echo
path A
Adaptive Filter
(128 ms)
PORT1
PORT2
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