参数资料
型号: ZL50232GD
厂商: ZARLINK SEMICONDUCTOR INC
元件分类: 数字传输电路
英文描述: DATACOM, ISDN ECHO CANCELLER, PBGA208
封装: 17 X 17 MM, 1.30 MM HEIGHT, LBGA-208
文件页数: 28/41页
文件大小: 809K
代理商: ZL50232GD
ZL50232
Data Sheet
34
Zarlink Semiconductor Inc.
Power-up
0Chex
ECA: Non-Linear Processor Threshold Register 2
(NLPTHR)
R/W Address:
19hex + Base Address
ECB: Non-Linear Processor Threshold Register 2
(NLPTHR)
R/W Address:
39hex + Base Address
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
NLP15
NLP14
NLP13
NLP12
NLP11
NLP10
NLP9
NLP8
Power-up
E0hex
ECA: Non-Linear Processor Threshold Register 1
(NLPTHR)
R/W Address:
18hex + Base Address
ECB: Non-Linear Processor Threshold Register 1
(NLPTHR)
R/W Address:
38hex + Base Address
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
NLP7
NLP6
NLP5
NLP4
NLP3
NLP2
NLP1
NLP0
Functional Description of Register Bits
This register allows the user to program the level of the Non-Linear Processor Threshold (NLPTHR). The 16 bit
2’s complement linear value defaults to 0CE0hex = 0.1 or -20.0 dB. The maximum value is 7FFFhex = 0.9999 or
0 dB. The high byte is in Register 2 and the low byte is in Register 1.
Power-up
40hex
ECA: Adaptation Step Size Register 2 (MU)
R/W Address:
1Bhex + Base Address
ECB: Adaptation Step Size Register 2 (MU)
R/W Address:
3Bhex + Base Address
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
MU15
MU14
MU13
MU12
MU11
MU10
MU9
MU8
Power-up
00hex
ECA: Adaptation Step Size Register 1 (MU)
R/W Address:
1Ahex + Base Address
ECB: Adaptation Step Size Register 1 (MU)
R/W Address:
3Ahex + Base Address
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
MU7
MU6
MU5
MU4
MU3
MU2
MU1
MU0
Functional Description of Register Bits
This register allows the user to program the level of MU. MU is a 16 bit 2’s complement value which defaults to
4000hex = 1.0 The maximum value is 7FFFhex or 1.9999 decimal. The high byte is in Register 2 and the low byte
is in Register 1.
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