- 您现在的位置：买卖IC网 > PDF目录300164 > ZL50114GAG2 (XILINX INC) SPECIALTY TELECOM CIRCUIT, PBGA552 PDF资料下载
参数资料
| 型号： | ZL50114GAG2 |
| 厂商： | XILINX INC |
| 元件分类： | 通信及网络 |
| 英文描述： | SPECIALTY TELECOM CIRCUIT, PBGA552 |
| 封装： | 35 X 35 MM, 1.27 MM PITCH, LEAD FREE, PLASTIC, MS-034, BGA-552 |
| 文件页数： | 79/113页 |
| 文件大小： | 2004K |
| 代理商： | ZL50114GAG2 |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页第52页第53页第54页第55页第56页第57页第58页第59页第60页第61页第62页第63页第64页第65页第66页第67页第68页第69页第70页第71页第72页第73页第74页第75页第76页第77页第78页当前第79页第80页第81页第82页第83页第84页第85页第86页第87页第88页第89页第90页第91页第92页第93页第94页第95页第96页第97页第98页第99页第100页第101页第102页第103页第104页第105页第106页第107页第108页第109页第110页第111页第112页第113页
ZL50110/11/12/14
Data Sheet
68
Zarlink Semiconductor Inc.
7.0
System Features
7.1
Latency
The following lists the intrinsic processing latency of the ZL50110/11/12/14, regardless of the number of active
channels or contexts.
TDM to Packet transmission processing latency less than 125
μs
Packet to TDM transmission processing latency less than 250
μs (unstructured)
Packet to TDM transmission processing latency less than 250
μs (structured, more than 16 channels in
context)
Packet to TDM transmission processing latency less than 375
μs (structured, 16 or less channels in context)
End-to-end latency may be estimated as the transmit latency + packet network latency + receive latency. The
transmit latency is the sum of the transmit processing and the number of frames per packet x 125
μs. The receive
latency is the sum of the receive processing and the delay through the jitter buffer which is programmed to
compensate for packet network PDV.
The ZL50110/11/12/14 is capable of creating an extremely low latency connection, with end to end delays of less
than 0.5 ms, depending on user configuration.
7.2
Loopback Modes
The ZL50110/11/12/14 devices support loopback of the TDM circuits and the circuit emulation packets.
TDM loopback is achieved by first packetizing the TDM circuit as normal via the TDM Interface and Payload
Assembly blocks. The packetized data is then routed by the Task Manager back to the same TDM port via the TDM
Formatter and TDM Interface.
Loopback of the emulated services is achieved by redirecting classified packets from the Packet Receive blocks,
back to the packet network. The Packet Transmit blocks are setup to strip the original header and add a new
header directing the packets back to the source.
7.3
Host Packet Generation
The control processor can generate packets directly, allowing it to use the network for out-of-band communications.
This can be used for transmission of control data or network setup information, e.g., routing information. The host
interface can also be used by a local resource for network transmission of processed data.
The device supports dual address DMA transfers of packets to and from the CPU memory, using the host's own
DMA controller. Table 27 illustrates the maximum bandwidths achievable by an external DMA master.
Note 1:
Maximum bandwidths are the maximum the ZL50110/11/12/14 devices can transfer under host control, and assumes only
minimal packet processing by the host.
Note 2:
Combined figures assume the same amount of data is to be transferred each way.
Note 3:
DMA with external memory must use single packet mode. Refer to ZL5011x Design Manual for details.
DMA Path
Packet Size
Max Bandwidth Mbps1
ZL50110/11/12/14 to CPU only
>1000 bytes
50
ZL50110/11/12/14 to CPU only
60 bytes
6.7
CPU to ZL50110/11/12/14 only
>1000 bytes
60
CPU to ZL50110/11/12/14 only
60 bytes
43
Combined2
>1000 bytes
58 (29 each way)
Combined2
60 bytes
11 (5.5 each way)
Table 27 - DMA Maximum Bandwidths
相关PDF资料 |
PDF描述 |
|---|---|
| ZL50114GAG | SPECIALTY TELECOM CIRCUIT, PBGA552 |
| ZL50232GD | DATACOM, ISDN ECHO CANCELLER, PBGA208 |
| ZL50233/GDG | DATACOM, ISDN ECHO CANCELLER, PBGA208 |
| ZL50408GDC | DATACOM, LAN SWITCHING CIRCUIT, PBGA208 |
| ZL50408GDG2 | DATACOM, LAN SWITCHING CIRCUIT, PBGA208 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| ZL50115 | 制造商:ZARLINK 制造商全称:Zarlink Semiconductor Inc 功能描述:32, 64 and 128 Channel CESoP Processors |
| ZL50115GAG | 制造商:Microsemi Corporation 功能描述:SWIT FABRIC 1K X 1K 1.8V/3.3V 324BGA - Trays 制造商:Microsemi Corporation 功能描述:IC CESOP PROCESSOR 32CH 324PBGA |
| ZL50115GAG2 | 制造商:Microsemi Corporation 功能描述:PB FREE 1 TDM + 1 ETHERNET - Trays 制造商:Microsemi Corporation 功能描述:IC CESOP PROCESSOR 32CH 324PBGA |
| ZL50116 | 制造商:ZARLINK 制造商全称:Zarlink Semiconductor Inc 功能描述:32, 64 and 128 Channel CESoP Processors |
| ZL50116GAG | 制造商:Microsemi Corporation 功能描述:2 TDM + 1 ETHERNET - Trays 制造商:MICROSEMI CONSUMER MEDICAL PRODUCT GROUP 功能描述:IC CESOP PROCESSOR 64CH 324PBGA 制造商:Microsemi Corporation 功能描述:IC CESOP PROCESSOR 64CH 324PBGA |
发布紧急采购，3分钟左右您将得到回复。