参数资料
型号: ZL50114GAG2
厂商: XILINX INC
元件分类: 通信及网络
英文描述: SPECIALTY TELECOM CIRCUIT, PBGA552
封装: 35 X 35 MM, 1.27 MM PITCH, LEAD FREE, PLASTIC, MS-034, BGA-552
文件页数: 86/113页
文件大小: 2004K
代理商: ZL50114GAG2
ZL50110/11/12/14
Data Sheet
74
Zarlink Semiconductor Inc.
7.11
Test Modes Operation
7.11.1
Overview
The ZL50110/11/12/14 family supports the following modes of operation.
7.11.1.1
System Normal Mode
This mode is the device's normal operating mode. Boundary scan testing of the peripheral ring is accessible in this
mode via the dedicated JTAG pins. The JTAG interface is compliant with the IEEE Std. 1149.1-2001; Test Access
Port and Boundary Scan Architecture.
Each variant has it's own dedicated.bsdl file which fully describes it's boundary scan architecture.
7.11.1.2
System Tri-State Mode
All output and I/O output drivers are tri-stated allowing the device to be isolated when testing or debugging the
development board.
7.11.2
Test Mode Control
The System Test Mode is selected using the dedicated device input bus TEST_MODE[2:0] as follows in Table 28.
7.11.3
System Normal Mode
Selected by TEST_MODE[2:0] = 3'b000. As the test_mode[2:0] inputs have internal pull-downs this is the default
mode of operation if no external pull-up/downs are connected. The GPIO[15:0] bus is captured on the rising edge of
the external reset to provide internal bootstrap options. After the internal reset has been de-asserted the GPIO pins
may be configured by the ADM module as either inputs or outputs.
7.11.4
System Tri-state Mode
Selected by TEST_MODE[2:0] = 3'b011. All device output and I/O output drivers are tri-stated.
System Test Mode
test_mode[2:0]
SYS_NORMAL_MODE
3’b000
SYS_TRI_STATE_MODE
3’b011
Table 28 - Test Mode Control
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