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| 型号： | ZL50114GAG2 |
| 厂商： | XILINX INC |
| 元件分类： | 通信及网络 |
| 英文描述： | SPECIALTY TELECOM CIRCUIT, PBGA552 |
| 封装： | 35 X 35 MM, 1.27 MM PITCH, LEAD FREE, PLASTIC, MS-034, BGA-552 |
| 文件页数： | 3/113页 |
| 文件大小： | 2004K |
| 代理商： | ZL50114GAG2 |
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ZL50110/11/12/14
Data Sheet
100
Zarlink Semiconductor Inc.
11.9
System Function Port
Note 1:
The system clock frequency stability affects the holdover-operating mode of the DPLL. Holdover Mode is typically used for a
short duration while network synchronisation is temporarily disrupted. Drift on the system clock directly affects the Holdover
Mode accuracy. Note that the absolute system clock accuracy does not affect the Holdover accuracy, only the change in the
system clock (SYSTEM_CLK) accuracy while in Holdover. For example, if the system clock oscillator has a temperature
coefficient of 0.1 ppm/C, a 10C change in temperature while the DPLL is in will result in a frequency accuracy offset of
1ppm. The intrinsic frequency accuracy of the DPLL Holdover Mode is 0.06 ppm, excluding the system clock drift.
Note 2:
The system clock frequency affects the operation of the DPLL in free-run mode. In this mode, the DPLL provides timing and
synchronisation signals which are based on the frequency of the accuracy of the master clock (i.e. frequency of clock output
equals 8.192 MHz ± SYSTEM_CLK accuracy ± 0.005 ppm).
Note 3:
The absolute SYSTEM_CLK accuracy must be controlled to ± 30 ppm in synchronous master mode to enable the internal
DPLL to function correctly.
Note 4:
In asynchronous mode and in synchronous slave mode the DPLL is not used. Therefore the tolerance on SYSTEM_CLK may
be relaxed slightly.
Note 5:
The quality of SYSTEM_CLK, or the oscillator that drives SYSTEM_CLK directly impacts the adaptive clock recovery
performance. See Section 6.3.
Parameter
Symbol
Min.
Typ.
Max.
Units
Notes
SYSTEM_CLK Frequency
CLKFR
-
100
-
MHz
Note 1, Note 2
and Note 5
SYSTEM_CLK accuracy
(synchronous master mode)
CLKACS
-
±30
ppm
Note 3
SYSTEM_CLK accuracy
(synchronous slave mode and
asynchronous mode)
CLKACA
-
±200
ppm
Note 4
Table 43 - System Clock Timing
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相关代理商/技术参数 |
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| ZL50115 | 制造商:ZARLINK 制造商全称:Zarlink Semiconductor Inc 功能描述:32, 64 and 128 Channel CESoP Processors |
| ZL50115GAG | 制造商:Microsemi Corporation 功能描述:SWIT FABRIC 1K X 1K 1.8V/3.3V 324BGA - Trays 制造商:Microsemi Corporation 功能描述:IC CESOP PROCESSOR 32CH 324PBGA |
| ZL50115GAG2 | 制造商:Microsemi Corporation 功能描述:PB FREE 1 TDM + 1 ETHERNET - Trays 制造商:Microsemi Corporation 功能描述:IC CESOP PROCESSOR 32CH 324PBGA |
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