参数资料
型号: ZL50114GAG2
厂商: XILINX INC
元件分类: 通信及网络
英文描述: SPECIALTY TELECOM CIRCUIT, PBGA552
封装: 35 X 35 MM, 1.27 MM PITCH, LEAD FREE, PLASTIC, MS-034, BGA-552
文件页数: 46/113页
文件大小: 2004K
代理商: ZL50114GAG2
ZL50110/11/12/14
Data Sheet
38
Zarlink Semiconductor Inc.
MII Port 1
Signal
I/O
Package Balls
Description
M1_LINKUP_LED
O
G23 on ZL50110/4
F26 on ZL50111/2
LED drive for MAC 1 to indicate port is linked
up.
Logic 0 output = LED on
Logic 1 output = LED off
M1_ACTIVE_LED
O
AB25
LED drive for MAC 1 to indicate port is
transmitting or receiving packet data.
Logic 0 output = LED on
Logic 1 output = LED off
M1_GIGABIT_LED
O
G25
LED drive for MAC 1 to indicate operation at
Gbps.
Logic 0 output = LED on
Logic 1 output = LED off
M1_REFCLK
I D
M22
GMII/TBI - Reference Clock input at
125 MHz. Can be used to lock receive
circuitry (RX) to M1_GTXCLK rather than
recovering the RXCLK (or RBC0 and
RBC1). Useful, for example, in the absence
of valid serial data.
NOTE: In MII mode this pin must be driven
with the same clock as M1_RXCLK.
M1_RXCLK
I U
M23
GMII/MII - M1_RXCLK.
Accepts the following frequencies:
25.0 MHz
MII
100 Mbps
125.0 MHz
GMII 1 Gbps
M1_RBC0
I U
U26
TBI - M1_RBC0.
Used as a clock when in TBI mode. Accepts
62.5 MHz and is 180°C out of phase with
M1_RBC1.
Receive data is clocked at
each rising edge of M1_RBC1 and
M1_RBC0, resulting in 125 MHz sample
rate.
M1_RBC1
I U
T25
TBI - M1_RBC1
Used as a clock when in TBI mode. Accepts
62.5 MHz, and is 180° out of phase with
M1_RBC0. Receive data is clocked at each
rising edge of M1_RBC1 and M1_RBC0,
resulting in 125 MHz sample rate.
M1_COL
I D
R25
GMII/MII - M1_COL.
Collision Detection. This signal is
independent of M1_TXCLK and
M1_RXCLK, and is asserted when a
collision is detected on an attempted
transmission. It is active high, and only
specified for half-duplex operation.
Table 11 - MII Port 1 Interface Package Ball Definition
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