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参数资料
| 型号： | ZL50114GAG2 |
| 厂商： | XILINX INC |
| 元件分类： | 通信及网络 |
| 英文描述： | SPECIALTY TELECOM CIRCUIT, PBGA552 |
| 封装： | 35 X 35 MM, 1.27 MM PITCH, LEAD FREE, PLASTIC, MS-034, BGA-552 |
| 文件页数： | 72/113页 |
| 文件大小： | 2004K |
| 代理商： | ZL50114GAG2 |
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ZL50110/11/12/14
Data Sheet
61
Zarlink Semiconductor Inc.
5.3.3
TDM Clock Structure
The TDM interface can operate in two modes, synchronous for structured TDM data, and asynchronous for
unstructured TDM data. The ZL50110/11/12/14 is capable of providing the TDM clock for either of the modes. The
ZL50110/11/12/14 supports clock recovery in both synchronous and asynchronous modes of operation. In
asynchronous operation each stream may have independent clock recovery.
5.3.3.1
Synchronous TDM Clock Generation
In synchronous mode all 32 streams will be driven by a common clock source. When the ZL50110/11/12/14 is
acting as a master device, the source can either be the internal DPLL or an external PLL. In both cases, the primary
and secondary reference clocks are taken from either two TDM input clocks, or two external clock sources driven to
the chip. The input clocks are then divided down where necessary and sent either to the internal DPLL or to the
output pins for connection to an external DPLL. The DPLL then provides the common clock and frame pulse
required to drive the TDM streams. See “DPLL Specification” on page 75 for further details.
Figure 14 - Synchronous TDM Clock Generation
When the ZL50110/11/12/14 is acting as a slave device, the common clock and frame pulse signals are taken from
an external device providing the TDM master function.
5.3.3.2
Asynchronous TDM Clock Generation
Each stream uses a separate internal DCO to provide an asynchronous TDM clock output. The DCO can be
controlled to recover the clock from the original TDM source depending on the timing algorithm used.
5.4
Payload Assembly
Data traffic received on the TDM Access Interface is sampled in the TDM Interface block, and synchronized to the
internal clock. It is then forwarded to the payload assembly process. The ZL50110/11/12/14 Payload Assembler can
handle up to 128 active packet streams or “contexts” simultaneously. Packet payloads are assembled in the format
shown in Figure 15 - on page 62. This meets the requirements of the IETF CESoPSN standard (RFC 5086).
Alternatively, packet payloads are assembled in the format shown in Figure 17 - on page 63. This meets the
requirements of the IETF SAToP standard (RFC 4553).
The Packet Transmit (PTX) circuit adds Layer 2 and Layer 3 protocol headers. The chosen protocol header
combination for addition by the PTX must not exceed 64 bytes. The exception is context 127 (the 128th context),
which must not exceed 56 bytes.
FRAME
CLOCK
TDM_CLKi[31:0]
PLL_SE
C
PLL_PRI
SRS
SRD
DIV
Internal
DPLL
PRS
PRD
TDM_CLKiP
TDM_CLKiS
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相关代理商/技术参数 |
参数描述 |
|---|---|
| ZL50115 | 制造商:ZARLINK 制造商全称:Zarlink Semiconductor Inc 功能描述:32, 64 and 128 Channel CESoP Processors |
| ZL50115GAG | 制造商:Microsemi Corporation 功能描述:SWIT FABRIC 1K X 1K 1.8V/3.3V 324BGA - Trays 制造商:Microsemi Corporation 功能描述:IC CESOP PROCESSOR 32CH 324PBGA |
| ZL50115GAG2 | 制造商:Microsemi Corporation 功能描述:PB FREE 1 TDM + 1 ETHERNET - Trays 制造商:Microsemi Corporation 功能描述:IC CESOP PROCESSOR 32CH 324PBGA |
| ZL50116 | 制造商:ZARLINK 制造商全称:Zarlink Semiconductor Inc 功能描述:32, 64 and 128 Channel CESoP Processors |
| ZL50116GAG | 制造商:Microsemi Corporation 功能描述:2 TDM + 1 ETHERNET - Trays 制造商:MICROSEMI CONSUMER MEDICAL PRODUCT GROUP 功能描述:IC CESOP PROCESSOR 64CH 324PBGA 制造商:Microsemi Corporation 功能描述:IC CESOP PROCESSOR 64CH 324PBGA |
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