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参数资料
| 型号： | ZL50114GAG2 |
| 厂商： | XILINX INC |
| 元件分类： | 通信及网络 |
| 英文描述： | SPECIALTY TELECOM CIRCUIT, PBGA552 |
| 封装： | 35 X 35 MM, 1.27 MM PITCH, LEAD FREE, PLASTIC, MS-034, BGA-552 |
| 文件页数： | 49/113页 |
| 文件大小： | 2004K |
| 代理商： | ZL50114GAG2 |
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ZL50110/11/12/14
Data Sheet
40
Zarlink Semiconductor Inc.
M1_TXER /
M1_TXD[9]
O
N23
GMII/MII - M1_TXER
Transmit Error. Transmitted synchronously
with respect to M1_TXCLK, and active high.
When asserted (with M1_TXEN also
asserted) the ZL50110/11/12/14 will transmit
a non-valid symbol, somewhere in the
transmitted frame.
TBI - M1_TXD[9]
Transmit Data. Clocked on rising edge of
M1_GTXCLK.
M1_GTX_CLK
O
N21
GMII/TBI only - Gigabit Transmit Clock
Output of a clock for Gigabit operation at
125 MHz.
MII Port 2 - ZL50111 and ZL50112 variants only.
Note: This port must not be used to receive data at the same time as port 3,
they are mutually exclusive.
Signal
I/O
Package Balls
Description
M2_LINKUP_LED
O
G23
LED drive for MAC 2 to indicate port is
linked up.
Logic 0 output = LED on
Logic 1 output = LED off
M2_ACTIVE_LED
O
AB24
LED drive for MAC 2 to indicate port is
transmitting or receiving packet data.
Logic 0 output = LED on
Logic 1 output = LED off
M2_RXCLK
I U
AA19
MII only - Receive Clock.
Accepts the following frequencies:
25.0 MHz
MII
100 Mbps
M2_COL
I D
AE26
Collision Detection. This signal is
independent of M2_TXCLK and
M2_RXCLK, and is asserted when a
collision is detected on an attempted
transmission. It is active high, and only
specified for half-duplex operation.
M2_RXD[3:0]
I U
[3]
AD25
[1]
AB21
[2]
AC23
[0]
AD24
Receive Data. Clocked on rising edge of
M2_RXCLK.
M2_RXDV
I D
AA20
Receive Data Valid. Active high. This signal
is clocked on the rising edge of M2_RXCLK.
It is asserted when valid data is on the
M2_RXD bus.
Table 12 - MII Port 2 Interface Package Ball Definition
MII Port 1
Signal
I/O
Package Balls
Description
Table 11 - MII Port 1 Interface Package Ball Definition (continued)
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相关代理商/技术参数 |
参数描述 |
|---|---|
| ZL50115 | 制造商:ZARLINK 制造商全称:Zarlink Semiconductor Inc 功能描述:32, 64 and 128 Channel CESoP Processors |
| ZL50115GAG | 制造商:Microsemi Corporation 功能描述:SWIT FABRIC 1K X 1K 1.8V/3.3V 324BGA - Trays 制造商:Microsemi Corporation 功能描述:IC CESOP PROCESSOR 32CH 324PBGA |
| ZL50115GAG2 | 制造商:Microsemi Corporation 功能描述:PB FREE 1 TDM + 1 ETHERNET - Trays 制造商:Microsemi Corporation 功能描述:IC CESOP PROCESSOR 32CH 324PBGA |
| ZL50116 | 制造商:ZARLINK 制造商全称:Zarlink Semiconductor Inc 功能描述:32, 64 and 128 Channel CESoP Processors |
| ZL50116GAG | 制造商:Microsemi Corporation 功能描述:2 TDM + 1 ETHERNET - Trays 制造商:MICROSEMI CONSUMER MEDICAL PRODUCT GROUP 功能描述:IC CESOP PROCESSOR 64CH 324PBGA 制造商:Microsemi Corporation 功能描述:IC CESOP PROCESSOR 64CH 324PBGA |
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