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参数资料
| 型号： | ZL50114GAG2 |
| 厂商： | XILINX INC |
| 元件分类： | 通信及网络 |
| 英文描述： | SPECIALTY TELECOM CIRCUIT, PBGA552 |
| 封装： | 35 X 35 MM, 1.27 MM PITCH, LEAD FREE, PLASTIC, MS-034, BGA-552 |
| 文件页数： | 51/113页 |
| 文件大小： | 2004K |
| 代理商： | ZL50114GAG2 |
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ZL50110/11/12/14
Data Sheet
42
Zarlink Semiconductor Inc.
M3_RXCLK
I U
K26
MII only - Receive Clock.
Accepts the following frequencies:
25.0 MHz
MII
100 Mbps
M3_COL
I D
J26
Collision Detection. This signal is
independent of M3_TXCLK and
M3_RXCLK, and is asserted when a
collision is detected on an attempted
transmission. It is active high, and only
specified for half-duplex operation.
M3_RXD[3:0]
I U
[3]
J22
[1]
J24
[2]
J23
[0]
J25
Receive Data. Clocked on rising edge of
M3_RXCLK.
M3_RXDV
I D
J21
Receive Data Valid. Active high. This signal
is clocked on the rising edge of M3_RXCLK.
It is asserted when valid data is on the
M3_RXD bus.
M3_RXER
I D
H26
Receive Error. Active high signal indicating
an error has been detected. Normally valid
when M3_RXDV is asserted. Can be used
in conjunction with M3_RXD when
M3_RXDV signal is de-asserted to indicate
a False Carrier.
M3_CRS
I D
H24
Carrier Sense. This asynchronous signal is
asserted when either the transmission or
reception device is non-idle. It is active
high.
M3_TXCLK
I U
H25
MII only - Transmit Clock
Accepts the following frequencies:
25.0 MHz
MII
100 Mbps
M3_TXD[3:0]
O
[3]
K23
[1]
L25
[2]
L26
[0]
L24
Transmit Data. Clocked on rising edge of
M3_TXCLK.
M3_TXEN
O
K24
Transmit Enable. Asserted when the MAC
has data to transmit, synchronously to
M3_TXCLK with the first pre-amble of the
packet to be sent. Remains asserted until
the end of the packet transmission. Active
high.
M3_TXER
O
K25
Transmit Error. Transmitted synchronously
with respect to M3_TXCLK, and active high.
When asserted (with M3_TXEN also
asserted) the ZL50111 will transmit a
non-valid symbol, somewhere in the
transmitted frame.
MII Port 3 - ZL50111 variant only
Note: This port must not be used to receive data at the same time as port 2,
they are mutually exclusive.
Signal
I/O
Package Balls
Description
Table 13 - MII Port 3 Interface Package Ball Definition (continued)
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相关代理商/技术参数 |
参数描述 |
|---|---|
| ZL50115 | 制造商:ZARLINK 制造商全称:Zarlink Semiconductor Inc 功能描述:32, 64 and 128 Channel CESoP Processors |
| ZL50115GAG | 制造商:Microsemi Corporation 功能描述:SWIT FABRIC 1K X 1K 1.8V/3.3V 324BGA - Trays 制造商:Microsemi Corporation 功能描述:IC CESOP PROCESSOR 32CH 324PBGA |
| ZL50115GAG2 | 制造商:Microsemi Corporation 功能描述:PB FREE 1 TDM + 1 ETHERNET - Trays 制造商:Microsemi Corporation 功能描述:IC CESOP PROCESSOR 32CH 324PBGA |
| ZL50116 | 制造商:ZARLINK 制造商全称:Zarlink Semiconductor Inc 功能描述:32, 64 and 128 Channel CESoP Processors |
| ZL50116GAG | 制造商:Microsemi Corporation 功能描述:2 TDM + 1 ETHERNET - Trays 制造商:MICROSEMI CONSUMER MEDICAL PRODUCT GROUP 功能描述:IC CESOP PROCESSOR 64CH 324PBGA 制造商:Microsemi Corporation 功能描述:IC CESOP PROCESSOR 64CH 324PBGA |
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