参数资料
型号: ZL50114GAG2
厂商: XILINX INC
元件分类: 通信及网络
英文描述: SPECIALTY TELECOM CIRCUIT, PBGA552
封装: 35 X 35 MM, 1.27 MM PITCH, LEAD FREE, PLASTIC, MS-034, BGA-552
文件页数: 71/113页
文件大小: 2004K
代理商: ZL50114GAG2
ZL50110/11/12/14
Data Sheet
60
Zarlink Semiconductor Inc.
5.3.2
Structured TDM Port Data Formats
The ZL50110/11/12/14 is programmable such that the frame/clock polarity and clock alignment can be set to any
desired combination. Table 26 shows a brief summary of four different TDM formats; ST-BUS, H.110, H-MVIP, and
Generic (synchronous mode only), for more information see the relevant specifications shown. There are many
additional formats for TDM transmission not depicted in Table 26, but the flexibility of the port will cover almost any
scenario. The overall data format is set for the entire TDM Interface device, rather than on a per stream basis. It is
possible to control the polarity of the master clock and frame pulse outputs, independent of the chosen data format
(used when operating in synchronous master mode).
Data
Format
Data
Rate
(Mbps)
Number
of
channels
per
frame
Clock
Freq.
(MHz)
Nominal
Frame
Pulse
Width
(ns)
Frame
Pulse
Polarity
Frame Boundary
Alignment
Standard
clock
frame
pulse
ST-bus
2.048
32
2.048
244
Negative
Rising
Edge
Straddles
boundary
MSAN-126
Rev B
(Issue 4)
Zarlink
2.048
32
4.096
244
Negative
Falling
Edge
Straddles
boundary
8.192
128
16.384
61
Negative
Falling
Edge
Straddles
boundary
H.110
8.192
128
8.192
122
Negative
Rising
edge
Straddles
boundary
ECTF
H.110
H-MVIP
2.048
32
2.048
244
Negative
Rising
Edge
Straddles
boundary
H-MVIP
Release
1.1a
2.048
32
4.096
244
Negative
Falling
Edge
Straddles
boundary
8.192
128
16.384
244
Negative
Falling
Edge
Straddles
boundary
Generic
2.048
32
2.048
488
Positive
Rising
Edge
Rising
edge of
clock
8.192
128
8.192
122
Positive
Rising
Edge
Rising
edge of
clock
Table 26 - Some of the TDM Port Formats Accepted by the ZL50110/11/12/14 Family
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