参数资料
型号: ZL50112GAG
厂商: ZARLINK SEMICONDUCTOR INC
元件分类: 通信及网络
英文描述: SPECIALTY TELECOM CIRCUIT, PBGA552
封装: 35 X 35 MM, 1.27 MM, PLASTIC, BGA-552
文件页数: 113/113页
文件大小: 1923K
代理商: ZL50112GAG
ZL50110/11/12/14
Data Sheet
99
Zarlink Semiconductor Inc.
Figure 45 - CPU DMA Read - MPC8260
Figure 46 - CPU DMA Write - MPC8260
tOTV
tCTV
tOTV
tSDV
tODV
tCDV
tSDV
tODV
tCWV
tCTH
tCTS
tCEH
tCES
tCSH
tCSS
tCKH
tCKS
0 or more cycles
tCC
Note 1: CPU_SDACK2 must be asserted during the cycle shown. It may then be deasserted at any time. CPU_DATA is valid
when CPU_TA is asserted (always timed as shown). CPU_DATA will remain valid while CPU_CS and CPU_OE are asserted.
CPU_TA will continue to be driven until CPU_CS is deasserted.
CPU_CS and CPU_OE must BOTH be asserted to enable
CPU_CLK
CPU_DREQ1
CPU_SDACK2
CPU_CS
CPU_OE
CPU_WE
CPU_TS_ALE
CPU_DATA[31:0]
CPU_TA
the CPU_DATA output.
Note 2: CPU_DREQ1 shown with positive polarity
CPU_SDACK1 shown with negative polarity
tOTV
tCTV
tOTV
tCWV
tCDH
tCDS
tCTH
tCTS
tCEH
tCES
tCSH
tCSS
tCKH
tCKS
0 or more cycles
tCC
Note 1: CPU_SDACK1 must be asserted during the cycle shown. It may then be deasserted at any time.
Following assertion of CPU_TA (always timed as shown), CPU_CS may be deasserted. The MPC8260
will continue to assert CPU_CS until CPU_TA has been synchronized internally. CPU_TA will continue
to be driven until CPU_CS is finally deasserted. During continued assertion of CPU_CS, CPU_WE and
CPU_DATA may be removed.
CPU_CLK
CPU_DREQ0
CPU_SDACK1
CPU_CS
CPU_OE
CPU_WE
CPU_TS_ALE
CPU_DATA[31:0]
CPU_TA
Note 2: CPU_DREQ0 shown with positive polarity
CPU_SDACK1 shown with negative polarity
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