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参数资料
| 型号： | ZL50418/GKC |
| 厂商： | ZARLINK SEMICONDUCTOR INC |
| 元件分类： | 网络接口 |
| 英文描述： | DATACOM, LAN SWITCHING CIRCUIT, PBGA553 |
| 封装： | 37.50 X 37.50 MM, 2.33 MM HEIGHT, MS-034, HSBGA-553 |
| 文件页数： | 79/155页 |
| 文件大小： | 1928K |
| 代理商： | ZL50418/GKC |
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ZL50418
Data Sheet
3
Zarlink Semiconductor Inc.
Description
The ZL50418 is a high density, low cost, high performance, non-blocking Ethernet switch chip. A single chip
provides 16 ports at 10/100 Mbps, 2 ports at 1000 Mbps and a CPU interface for managed and unmanaged switch
applications. The Gigabit ports can also support 10/100 M.
The chip supports up to 64K MAC addresses and up to 255 tagged-based Virtual LANs (VLANs). The centralized
shared memory architecture permits a very high performance packet forwarding rate at full wire speed. The chip is
optimized to provide low-cost, high-performance workgroup switching.
Two Frame Buffer Memory domains utilize cost-effective, high-performance synchronous SRAM with aggregate
bandwidth of 6.4 Gbps to support full wire speed on all ports simultaneously.
With delay bounded, strict priority, and/or WFQ transmission scheduling and WRED dropping schemes, the
ZL50418 provides powerful QoS functions for various multimedia and mission-critical applications. The chip
provides 4 transmission priorities (8 priorities per Gigabit port) and 2 levels of dropping precedence. Each packet is
assigned a transmission priority and dropping precedence based on the VLAN priority field in a VLAN tagged
frame, or the DS/TOS field, or the UDP/TCP logical port fields in IP packets. The ZL50418 recognizes a total of 16
UDP/TCP logical ports, 8 hard-wired and 8 programmable (including one programmable range).
The ZL50418 supports 3 groups of port trunking/load sharing. One group is dedicated to the two Gigabit ports, and
the other two groups to 10/100 ports, where each 10/100 group can contain up to 4 ports. Port trunking/load sharing
can be used to group ports between interlinked switches to increase the effective network bandwidth.
In half-duplex mode all ports support backpressure flow control to minimize the risk of losing data during long
activity bursts. In full-duplex mode, IEEE 802.3x flow control is provided. The ZL50418 also supports a per-system
option to enable flow control for best effort frames, even on QoS-enabled ports.
The Physical Coding Sublayer (PCS) is integrated on-chip to provide a direct 10-bit interface (TBI) for connection to
SERDES chips. The PCS can be bypassed to provide a GMII interface.
Statistical information for SNMP and the Remote Monitoring Management Information Base (RMON MIB) are
collected independently for all ports. Access to these statistical counters/registers is provided via the CPU interface.
SNMP Management frames can be received and transmitted via the CPU interface creating a complete network
management solution.
The ZL50418 is fabricated using 0.25 micron technology. Inputs, however, are 3.3 V tolerant, and the outputs are
capable of directly interfacing to LVTTL levels. The ZL50418 is packaged in a 553-pin Ball Grid Array package.
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