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参数资料
| 型号： | ZL50418/GKC |
| 厂商： | ZARLINK SEMICONDUCTOR INC |
| 元件分类： | 网络接口 |
| 英文描述： | DATACOM, LAN SWITCHING CIRCUIT, PBGA553 |
| 封装： | 37.50 X 37.50 MM, 2.33 MM HEIGHT, MS-034, HSBGA-553 |
| 文件页数： | 95/155页 |
| 文件大小： | 1928K |
| 代理商： | ZL50418/GKC |
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ZL50418
Data Sheet
44
Zarlink Semiconductor Inc.
The format of the Control Frame is described in the processor interface application note.
3.3
Unmanaged Mode
In unmanaged mode, the ZL50418 can be configured by EEPROM (24C02 or compatible) via an I2C interface at
boot time, or via a synchronous serial interface during operation.
3.3.1
I2C Interface
The IC interface serves the function of configuring the ZL50418 at boot time. The master is the ZL50418, and the
slave is the EEPROM memory.
The I2C interface uses two bus lines, a serial data line (SDA) and a serial clock line (SCL). The SCL line carries the
control signals that facilitate the transfer of information from EEPROM to the switch. Data transfer is 8-bit serial and
bidirectional at 50 Kbps. Data transfer is performed between master and slave IC using a request /
acknowledgment style of protocol. The master IC generates the timing signals and terminates data transfer. Figure
7 depicts the data transfer format. The slave address is the memory address of the EEPROM. Refer to “Register
Definition” on page 75 for IC address for each register.
Figure 7 - Data Transfer Format for I2C Interface
3.3.1.1
Start Condition
Generated by the master (in our case, the ZL50418). The bus is considered to be busy after the Start condition is
generated. The Start condition occurs if while the SCL line is High, there is a High-to-Low transition of the SDA line.
Other than in the Start condition (and Stop condition), the data on the SDA line must be stable during the High
period of SCL. The High or Low state of SDA can only change when SCL is Low. In addition, when the I2C bus is
free, both lines are High.
3.3.1.2
Address
The first byte after the Start condition determines which slave the master will select. The slave in our case is the
EEPROM. The first seven bits of the first data byte make up the slave address.
3.3.1.3
Data Direction
The eighth bit in the first byte after the Start condition determines the direction (R/W) of the message. A master
transmitter sets this bit to W; a master receiver sets this bit to R.
3.3.1.4
Acknowledgment
Like all clock pulses, the acknowledgment-related clock pulse is generated by the master. However, the transmitter
releases the SDA line (High) during the acknowledgment clock pulse. Furthermore, the receiver must pull down the
SDA line during the acknowledge pulse so that it remains stable Low during the High period of this clock pulse. An
acknowledgment pulse follows every byte transfer.
If a slave receiver does not acknowledge after any byte, then the master generates a Stop condition and aborts the
transfer.
If a master receiver does not acknowledge after any byte, then the slave transmitter must release the SDA line to let
the master generate the Stop condition.
START
SLAVE ADDRESS
R/W
ACK
DATA 1 (8 bits)
ACK
DATA 2
ACK
DATA M
ACK
STOP
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