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参数资料
| 型号： | ZL50418/GKC |
| 厂商： | ZARLINK SEMICONDUCTOR INC |
| 元件分类： | 网络接口 |
| 英文描述： | DATACOM, LAN SWITCHING CIRCUIT, PBGA553 |
| 封装： | 37.50 X 37.50 MM, 2.33 MM HEIGHT, MS-034, HSBGA-553 |
| 文件页数： | 89/155页 |
| 文件大小： | 1928K |
| 代理商： | ZL50418/GKC |
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ZL50418
Data Sheet
39
Zarlink Semiconductor Inc.
2.2.4
PHY Addresses
The table below provides an overview of the PHY addresses required for each port in order for the MDIO auto-
negotiation to work between the ZL50418 MAC and the PHY device. If a different PHY address is used, then the
port must be manually brought up and the PHY will need to be polled for link status via the MIIC/D registers.
2.3
Management Module
The CPU can send a control frame to access or configure the internal databases within the ZL50418 device. The
Management Module decodes the control frame and executes the functions requested by the CPU. The
management module then sends a response or acknowledgment back to the CPU.
This Module is only active in managed mode. In unmanaged mode, no control frame is accepted by the device.
2.4
Frame Engine
The main function of the frame engine is to forward a frame to its proper destination port or ports. When a frame
arrives, the frame engine parses the frame header (64 bytes) and formulates a switching request which is sent to
the search engine to resolve the destination port. The arriving frame is moved to the FDB. After receiving a switch
response from the search engine, the frame engine performs transmission scheduling based on the frame’s priority.
The frame engine forwards the frame to the MAC module when the frame is ready to be sent.
2.5
Search Engine
The search engine resolves the frame's destination port or ports by searching the appropriate ZL50418 databases.
To achieve its objective, the search engine may use the destination MAC address, IP multicast address (IP
multicast packet), and VLAN fields in the packet header. The search engine is also responsible for MAC and VLAN
learning, assignment of transmission priority based on IEEE 802.1p or IP TOS/DS fields, and port trunking
functions.
2.6
LED Interface
The LED interface provides a serial interface for carrying 16 + 2 port status signals. It can also provide direct status
pins (6) for the two Gigabit ports.
A serial output channel provides port status information from the ZL50418 chips. It requires three additional pins.
LED_CLK at 12.5 MHz
LED_SYN a sync pulse that defines the boundary between status frames
LED_DATA a continuous serial stream of data for all status LEDs that repeats once every frame time
A non-serial interface is also allowed, but in this case, only the Gigabit ports will have status LEDs.
MAC Port
PHY Address
GMAC Port 0
0x01
GMAC Port 1
0x02
RMAC Port 0
0x08
RMAC Port 1
0x09
...
RMAC Port 15
0x17
CMAC Port
N/A
Table 4 - PHY Addresses
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