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参数资料
| 型号： | ZL50418/GKC |
| 厂商： | ZARLINK SEMICONDUCTOR INC |
| 元件分类： | 网络接口 |
| 英文描述： | DATACOM, LAN SWITCHING CIRCUIT, PBGA553 |
| 封装： | 37.50 X 37.50 MM, 2.33 MM HEIGHT, MS-034, HSBGA-553 |
| 文件页数： | 99/155页 |
| 文件大小： | 1928K |
| 代理商： | ZL50418/GKC |
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ZL50418
Data Sheet
48
Zarlink Semiconductor Inc.
During scheduling, the TxQ manager treats the unicast queue and the multicast queue of the same class as one
logical queue. The older head of line of the two queues is forwarded first.
The port control requests a FCB release only after the EOF for the multicast frame has been read by all ports to
which the frame is destined.
4.3
Frame Forwarding To and From CPU
Frame forwarding from the CPU port to a regular transmission port is nearly the same as forwarding between
transmission ports. The only difference is that the physical destination port must be indicated in addition to the
destination MAC address.
Frame forwarding to the CPU port is nearly the same as forwarding to a regular transmission port. The only
difference is in frame scheduling. Instead of using the patent-pending Zarlink Semiconductor scheduling algorithms,
scheduling for the CPU port is simply based on strict priority. That is, a frame in a high priority queue will always be
transmitted before a frame in a lower priority queue. There are four output queues to the CPU and one receive
queue.
5.0
Memory Interface
5.1
Overview
The ZL50418 provides two 64-bit wide SRAM banks, SRAM Bank A and SRAM Bank B. Each DMA can read and
write from both bank A and bank B. The following figure provides an overview of the ZL50418 SRAM banks.
Figure 8 - SRAM Interface Block Diagram (DMAs for 10/100 Ports Only)
Because the bus for each bank is 64 bits wide, frames are broken into 8-byte granules, written to and read from
memory. The first 8-byte granule gets written to Bank A, the second 8-byte granule gets written to Bank B and so on
in alternating fashion. When reading frames from memory, the same procedure is followed, first from A, then from B
and so on.
The reading and writing from alternating memory banks can be performed with minimal waste of memory
bandwidth. What’s the worst case? For any speed port, in the worst case, a 1-byte-long EOF granule gets written to
SRAM
TX DMA
0-7
TX DMA
8-15
TX DMA
16-23
RX DMA
0-7
RX DMA
8-15
RX DMA
16-23
SRAM
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