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参数资料
| 型号： | ZL50418GKG2 |
| 厂商： | ZARLINK SEMICONDUCTOR INC |
| 元件分类： | 网络接口 |
| 英文描述： | DATACOM, LAN SWITCHING CIRCUIT, PBGA553 |
| 封装： | 37.50 X 37.50 MM, 2.33 MM HEIGHT, LEAD FREE, MS-034, HSBGA-553 |
| 文件页数： | 87/155页 |
| 文件大小： | 1928K |
| 代理商： | ZL50418GKG2 |
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ZL50418
Data Sheet
37
Zarlink Semiconductor Inc.
Figure 3 - SCANLINK and SCANCOL Status Diagram
2.2.2
GMII MAC Module (GMAC)
The 10/100/1000 M Media Access Control (MAC) module provides the necessary buffers and control interface
between the Frame Engine (FE) and the external physical device (PHY). The ZL50418 GMAC implements both
GMII and MII interface, which offers a simple migration from 10/100 M to 1000 M.
The GMAC of the ZL50418 meets the IEEE 802.3Z specification. It is able to operate in 10/100M either Half or Full
Duplex mode with a back pressure/flow control mechanism or in 1G Full duplex mode with flow control mechanism.
Furthermore, it will automatically retransmit upon collision for up to 16 total transmissions.
The PHY addresses for the two GMACs are 01h and 02h. These two ports are denoted as ports 25 (G0) and 26
(G1).
For fiber optics media, the ZL50418 implements the Physical Code Sublayer (PCS) interface. The PCS includes an
8B10B encoder and decoder, auto-negotiation and Ten Bit Interface (TBI)
2.2.2.1
Physical Coding Sublayer (PCS) Module
For the ZL50418, the 1000BASE-X PCS module is designed internally and may be utilized in the absence of GMII.
The PCS incorporates all the functions required by the GMII to include encoding (decoding) 8B GMII data to (from)
8B/10B TBI format for PHY communication and generating Collision Detect (COL) signals for half-duplex mode. It
also manages the auto-negotiation process by informing the management entity that the PHY is ready for
communications. The on-chip PCS may be disabled if a PCS block exists within the Gigabit PHY. The TBI interface
provides a uniform interface for all 1000 Mbps PHY implementations.
The PCS comprises the PCS Transmit, Synchronization, PCS Receive and auto-negotiation processes for
1000BASE-X.
The PCS Transmit process sends the TBI signals TXD[9:0] to the physical medium and generates the GMII
Collision Detect (COL) signal based on whether a reception is occurring simultaneously with transmission.
Additionally, the Transmit process generates an internal “transmitting” flag and monitors auto-negotiation to
determine whether to transmit data or to reconfigure the link.
The PCS Synchronization process determines whether or not the receive channel is operational.
The PCS Receive process receives the TBI signals RXD[9:0] from the physical medium, and generates the GMII
RXD[7:0] signals and the internal “receiving” flag for use by the Transmit processes.
scan_clk
scan_link/
scan_col
Drived by VTX260x
Drived by CPLD
25 cycles for link/
24 cycles for col
Total 32 cycles period
Drived by device
Drived by CPLD
Total 32 cycles period
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