参数资料
型号: ZPSD412A0-C-90UI
元件分类: 微控制器/微处理器
英文描述: 64K X 8 OTPROM, 40 I/O, PIA-GENERAL PURPOSE, PQFP80
封装: PLASTIC, TQFP-80
文件页数: 83/128页
文件大小: 433K
代理商: ZPSD412A0-C-90UI
PSD4XX Family
54
PSD4XX Family
9.3.10 Port A – Functionality and Structure
Port A is the most flexible of all the I/O ports. It can be configured to perform one or more
of the following functions:
t Standard MCU I/O Mode
t PLD I/O
t Address Out – latched address lines A[0-7] are assigned to pins PA[0-7].
t Address In – input port for other address lines, inputs can be latched by ALE.
t Peripheral I/O
Figure 27 shows the structure of a Port A pin. If the pin is configured as an output port,
the multiplexer selects one of its three inputs as output. If the pin is configured as an input,
the input connects to :
1. Data In Register as input in Standard MCU I/O Mode
or
2. PA Macrocell as PLD input
or
3. PA Macrocell through a latch latched by ALE, as Address In input.
9.3.11 Port B – Functionality and Structure
Port B is similar to Port A in structure. It can be configured to perform one or more of the
following functions:
t Standard MCU I/O Mode
t PLD I/O
t Address Out – address lines A[0-7] for 8-bit multiplexed bus or address lines
A[8-15] for 16-bit multiplexed bus are assigned to pins PB[0-7].
Figure 28 shows the structure of a Port B pin. If the pin is configured as an output port,
the multiplexer selects one of its three inputs as output. If the pin is configured as input,
the input connects to :
t Data In Register as input in Standard MCU I/O Mode
or
t PB Macrocell as PLD input
The PSD4XX
Architecture
(cont.)
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