参数资料
型号: ZPSD412A0-C-90UI
元件分类: 微控制器/微处理器
英文描述: 64K X 8 OTPROM, 40 I/O, PIA-GENERAL PURPOSE, PQFP80
封装: PLASTIC, TQFP-80
文件页数: 87/128页
文件大小: 433K
代理商: ZPSD412A0-C-90UI
9.3.12 Port C and Port D – Functionality and Structure
Ports C and D are identical in function and structure and each can be configured to perform
one or more of the following operating modes:
t Standard MCU I/O Mode
t PLD Input – direct input to ZPLD
(PSD4XXA2 and ZPSD4XXA2 Only)
t Address Out – latched address outputs
– Port C: A[0-7] are assigned to pins PC[0-7]
– Port D: A[0-7] for 8-bit multiplexed bus or A[8-15] for 16-bit multiplexed
bus are assigned to pins PD0-7]
t Data Port
– Port C: D[0-7] for 8-bit non-multiplexed bus
– Port D: D[8-15] for 16-bit non-multiplexed bus
t Open Drain – select CMOS or Open Drain driver
Figures 29 and 30 show the structure of a Port C or D pin. If the pin is configured as output
port, the multiplexer selects one of the two inputs as output. If the pin is configured as input,
the input connects to :
t Data In Register as input in the Standard MCU I/O Mode
or
t ZPLD input (PSD4XXA2 and ZPSD4XXA2 Only)
9.3.13 Port E – Functionality and Structure
Port E can be configured to perform one or more of the following functions:
t Standard MCU I/O Mode
t PLD I/O (PSD4XXA2 and ZPSD4XXA2 Only)
t Address Out – latched address lines A[0-7] are assigned to pins PE[0-7]
t Alternate Function In – in this mode, the inputs to Port E pins are:
– PE0
BHE or PSEN or WRH or UDS or SIZ0
– PE1 – ALE
– PE7
APD CLK :clock input for Automatic Power Down Counter
Figure 31 shows the structure of a Port E pin. The Control Logic block selects one of four
sources through the multiplexer for pin output. If the pin is configured as input, the input
goes to:
t Data In Register as input in Standard MCU I/O Mode
or
t PE Macrocell as PLD input (PSD4XXA2 and ZPSD4XXA2 Only)
or
t Alternate Function In
PSD4XX Family
57
PSD4XX Family
The PSD4XX
Architecture
(cont.)
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