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参数资料
| 型号： | ZPSD412A0-C-90UI |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 64K X 8 OTPROM, 40 I/O, PIA-GENERAL PURPOSE, PQFP80 |
| 封装： | PLASTIC, TQFP-80 |
| 文件页数： | 95/128页 |
| 文件大小： | 433K |
| 代理商： | ZPSD412A0-C-90UI |
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PSD4XX Family
65
PSD4XX Family
The PSD4XX
Architecture
(cont.)
Figure 34. Port A In Peripheral I/O Mode
RD
PSEL0
PSEL1
D0 – D7
WR
PA0 – PA7
9.4.5 Peripheral I/O
The Peripheral I/O Mode is one of the operating modes of Port A. In this mode, Port A
is connected to the data bus of peripheral devices. Port A is enabled only when
the microcontroller is accessing the devices, otherwise the Port is tri-stated. This feature
enables the microcontroller to access external devices without requiring buffers and
decoders. Figure 34 shows the structure of Port A in the Peripheral I/O Mode.
The memory address space occupied by the devices are defined by two signals: PSEL0
and PSEL1. The signals are direct outputs from the Decoding PLD (DPLD). Whenever any
of the signals is active, the Port A driver is enabled, and the direction of the data flow is
determined by the RD/WR signals.
The Peripheral I/O Mode and the peripheral select signals are configured and defined in the
PSDsoft Software (see the section on I/O Port for configuration). The PIO bit in the VM
Register (see Table 17) also needs to be set to “1” by the user to initialize the Peripheral I/O
Mode.
The Peripheral I/O mode can be used, for example, in DMA applications where the
microcontroller does not support DMA operations, such as tri-stating the address/data bus.
Figure 35 shows a block diagram of a microcontroller and PSD4XX based design that
makes use of this mode. In this application, the microcontroller has a multiplexed bus which
is connected to the ADIO port. The C and D ports connect to the peripheral address bus
and are both configured in Address Out Mode. Port A is configured in the Peripheral I/O
mode and is connected to the peripheral data bus. Ports B and E are used to generate
control signals.
During normal activity, the microcontroller has access to any peripheral (memory or I/O
device) through the PSD4XX device. When there is a DMA request, the
microcontroller tri-states the address bus on Ports C and D by writing a “0” to the port
Direction Registers. The DMA controller then takes over the data and address buses after
receiving acknowledgement from the microcontroller.
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| ZDVG10A | 7 SEG NUMERIC DISPLAY, GREEN, 10.16 mm |
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相关代理商/技术参数 |
参数描述 |
|---|---|
| ZPSD412A1-12J | 制造商:未知厂家 制造商全称:未知厂家 功能描述:Field-Programmable Peripheral |
| ZPSD412A1-12JI | 制造商:未知厂家 制造商全称:未知厂家 功能描述:Field-Programmable Peripheral |
| ZPSD412A1-12LI | 制造商:未知厂家 制造商全称:未知厂家 功能描述:Field-Programmable Peripheral |
| ZPSD412A1-12U | 制造商:未知厂家 制造商全称:未知厂家 功能描述:Field-Programmable Peripheral |
| ZPSD412A1-12UI | 制造商:未知厂家 制造商全称:未知厂家 功能描述:Field-Programmable Peripheral |
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