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| 型号： | 4450HG/3-K |
| 厂商： | EXAR CORP |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | MICROPROCESSOR, PBGA324 |
| 封装： | ROHS COMPLIANT, HSBGA-324 |
| 文件页数： | 28/92页 |
| 文件大小： | 780K |
| 代理商： | 4450HG/3-K |
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4450 – Data Sheet, DS-0131-06
Page 34
Hifn Confidential
6.2.1.1
GMAC GMII/TBI Pin Mappings (Host-side Only)
Table 6-3 contains five columns for the signal names and mapping for GMII and TBI mode.
The leftmost column contains the 4450 pin name, and the next four columns contain the
functional signal name, based on whether the port is defined as GMII or TBI, and whether
the port functions as a MAC or a PHY device. For each port, Table 6-3 maps the 4450 pin
names to the signal functions depending on the settings of the host_config[2:0] pins
illustrated in Table 6-1.
Please note in Table 6-3 that the directions of the data and control signals associated with
the terms “receive” and “transmit” depend on whether the port is a MAC or a PHY. For
example, “receive” relates to data and control signals that are outputs on the PHY and
inputs on the MAC. And “transmit” relates to data and control signals that are inputs on the
PHY and outputs on the MAC. For the clocks, in MII mode both receive and transmit clocks
are PHY driven. In GMII mode, the receive and transmit clocks are source driven. In TBI
mode, the two receive clocks are shared with the MII receive and transmit clocks, which
are both PHY driven; and the TBI transmit clock is shared with the GMII transmit clock.
In addition to the four GMII/TBI operating modes for each host port, there are two ports
indicated by “hx_” in Table 6-3, host-side port 0 (“hx” = “h0”), and host-side port 1 (“hx”
= “h1”).
Table 6-6 provides the functional signal names and mapping for the Network and Host
ports if it is desired to run in RGMII/RTBI mode.
Table 6-3. 4450 GMII/TBI MAC/PHY modes pin mappings (Host Side Only)
Pin Name
MAC-GMII
MAC-TBI
PHY-GMII
PHY-TBI
GMII Signal I/O
TBI Signal
I/O
GMII Signal
I/O
TBI Signal
I/O
hx_ctrl_1
hx_col
in
n/a
in
hx_col
NC
n/a
NC
hx_ctrl_0
hx_crs
in
hx_sigdet
in
hx_crs
NC
hx_sigdet
NC
hx_clk_2
hx_gtxclk
out
hx_txpmaclk
out
hx_rxclk
out
hx_rxpmaclk
out
hx_clk_1
hx_rxclk
in
hx_rxpmaclk1
in
hx_gtxclk
in
hx_txpmaclk
in
hx_clk_0
hx_txclk
in
hx_rxpmaclk0
in
hx_txclk
out
hx_rxpmaclk0
out
hx_bus1[9}
hx_rxer
in
hx_rxd9
in
hx_txer
in
hx_txd9
in
hx_bus1[8}
hx_rxdv
in
hx_rxd8
in
hx_txen
in
hx_txd8
in
hx_bus1_[7:0]
hx_rxd[7:0
]
in
hx_rxd[7:0]
in
hx_txd[7:0]
in
hx_txd[7:0]
in
hx_bus0[9}
hx_txer
out
hx_txd9
out
hx_rxer
out
hx_rxd9
out
hx_bus0[8]
hx_txen
out
hx_txd8
out
hx_rxdv
out
hx_rxd8
out
hx_bus0[7:0]
hx_txd[7:0
]
out
hx_txd[7:0]
out
hx_rxd[7:0]
out
hx_rxd[7:0]
out
Note
hx = h0 or h1
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