参数资料
型号: 4450HG/3-K
厂商: EXAR CORP
元件分类: 微控制器/微处理器
英文描述: MICROPROCESSOR, PBGA324
封装: ROHS COMPLIANT, HSBGA-324
文件页数: 59/92页
文件大小: 780K
代理商: 4450HG/3-K
4450 – Data Sheet, DS-0131-06
Page 62
Hifn Confidential
6.9 Power and Ground Pins
Table 6-25. Power and Ground pins (Sheet 1 of 2)
Signal Name
I/O Type
Description
vdde
Power
3.3V External I/O power (includes RMII VDD)
vddh
Power
I/O VDD for Host GMII (3.3V) or RGMII (1.5V or 2.5V)
If both host and network ports are configured for SERDES/
SGMII, it is acceptable to connect vddn and vddh to 3.3V.
This may save some PCB real estate and reduce the
component cost/count because a dedicated 2.5V power
supply not required.
vddi
Power
1.0V Internal Core Logic Power
vddn
Power
I/O VDD for Network RGMII (1.5V or 2.5V) Interface.
If both host and network ports are configured for SERDES/
SGMII, it is acceptable to connect vddn and vddh to 3.3V.
This may save some PCB real estate and reduce the
component cost/count because a dedicated 2.5V power
supply not required.
vddr
Power
DDR I/O power 1.8V (DDR2)
vdds
Power
SERDES VDD 1.0V
vdd_reserved
Input
3.3V Reference Voltage for PLL. This is a test pin used
during the manufacturing process.
vss
Ground
Ground for Core logic and I/O
vref[_ddr[2:0]
Input
DDR Voltage Reference for SSTL bi-directional I/O
0.9V for DDR2
vref_netw
Input
0.75V Network Side GMACs Reference Voltage
Should be tied to Ground if the 1.5V RGMII interface
option is NOT used.
vref_host
Input
0.75V Host Side GMACs Reference Voltage
Should be tied to Ground if the 1.5V RGMII interface
option is NOT used.
vttn_serdes
Input
SERDES Network driver termination voltage (A/B)
Variable depending on the Application
vttn_serdes (V)
VSW (ac, mV)
1.0
250
1.2
350
1.5
500
1.8
750
Provides a method for varying the voltage swing on the
Network side SERDES differential ouputs. 1V p-p
differential signaling is common, vttn_serdes is normally
tied to 1.5 V.
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4450HA/3-K MICROPROCESSOR, PBGA324
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