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参数资料
| 型号： | 5962R9855201VYC |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 32-BIT, 12 MHz, RISC MICROCONTROLLER, CQFP132 |
| 封装： | QFP-132 |
| 文件页数： | 20/64页 |
| 文件大小： | 1464K |
| 代理商： | 5962R9855201VYC |
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27
The interrupt architecture allows for the disabling and masking
of certain interrupts. Output Register Instruction OTR
Rd,ENBL and OTR Rd,DSBL control the disable and enable
of interrupts. The content of the Rd register is a “don’t care”
for these commands. Status Register bit 9 reflects the state of
interrupts (i.e., enabled or disabled). The Mask Register
provides the ability to mask the service of user selected
interrupts. Interrupts awaiting service are reflected in the PI
Register. Execution of Input Register and Output Register
Instructions INR Rd,PI, OTR Rd,PI and OTR Rd,RPI read,
write, and clear the PI Register. To latch an interrupt into the
PI Register the corresponding bit must be a logic zero before
the event occurs. An integral part of interrupt service should
include the clearing of the appropriate bit in the PI Register.
Section 2.2.1 shows an example of clearing the PI register.
6.1.1 Interrupt Status
The architecture of the UT69R000 allows for the disabling and
masking of interrupts. If the software cannot support interrupt
service the software can disable (i.e., not recognize) interrupts.
The disable feature will prevent the servicing of all interrupts
with the exception of power fail (PFAIL) and software interrupt
(USR2). The UT69R000 will log these interrupts into the PI
Register but does not alter program flow to the interrupt vector.
Re-enabling interrupts with a non-zero PI Register will result
in the UT69R000 vectoring to the highest priority interrupt. To
prevent the service of these interrupt clear the PI Register
before re-enabling interrupts.
The mask feature allows the software to select particular
interrupts for service while masking others. The selection of
interrupts, via the mask feature, for service is controlled
through the MK Register. Input Register and Output Register
Instructions INR Rd,MK and OTR Rd,MK read and write the
MK register. The mask feature prevents the servicing of all
interrupts with the exception of PFAIL and USR2. Similiar to
the disable feature, unmasking and interrupt with a non-zero
PI Register results in the vectoring to the appropriate interrupt
vector. Writing a logical zero into a Mask Register bit location
will prevent the recognition of the specific interrupt (i.e.,
mask). To un-mask all interrupts write FFFF (hex) to the MK
register.
To enable the UT69R000 interrupts architecture the software
program enables interrupts by executing instruction OTR
Rd,ENBL, followed by a write to the Mask Register, OTR
Rd,MK. Interrupts are enabled and disabled on the falling edge
of internal clock cycle CK1 (rising edge of CK2).
6.1.2 Interrupt Processing and Vectors
The occurrence of an enabled and non-masked interrupts
results in the altering of program flow. Interrupt processing
begins by saving the present Instruction Counter Register (IC)
in the Instruction Counter Save Register (ICS) followed by
automatic disabling of all interrupts (Status Register Bit 9
equals logic 0). The UT69R000 then loads the designated
interrupt vector location into the Instruction Counter. The
UT69R000 begins interrupt service by executing the code
residing at the interrupt vector location.
Interrupt vectors reside from memory location 400 (hex) to 43C
(hex). Each interrupt is assigned a vector with four memory
locations (see table 2). These four memory locations allow for
storage of the Instruction Counter Save Register (ICS) and a
jump (JC), branch (BR), or call (CALL) to the interrupt service
routine. An example is shown below.
ISR0_INT0:
408 (hex) INR xR0, ICS
409 (hex) CALL xR18, ISR0
40A (hex) ISR0
40B (hex) NOP
Table 2. Interrupt Instruction Counter
Load Location
INTERRUPT
NUMBER
LOCATION
(HEX)
MASK-
(Y/N)
CAN USER
DISABLE
(Y/N)
ABLE
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15*
0400
0404
0408
040C
0410
0414
0418
041C
0420
0424
0428
042C
0430
0434
0438
043C
N
Y
N
Y
N
Y
N
Y
* See note on page 11.
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